| 8229989 |
Method for controlling rounding modes in single instruction multiple data (SIMD) floating-point units |
Sang Hoo Dhong, Harm Peter Hofstee, Christian Jacobi, Silvia M. Mueller |
2012-07-24 |
| 8166085 |
Reducing the latency of sum-addressed shifters |
Sang Hoo Dhong, Christian Jacobi, Silvia M. Mueller, Hiroo Nishikawa |
2012-04-24 |
| 8131795 |
High speed adder design for a multiply-add based floating point unit |
Sang Hoo Dhong, Silvia M. Mueller |
2012-03-06 |
| 7490119 |
High speed adder design for a multiply-add based floating point unit |
Sang Hoo Dhong, Silvia M. Mueller |
2009-02-10 |
| 7469265 |
Methods and apparatus for performing multi-value range checks |
Sang Hoo Dhong, Silvia M. Mueller, Hiroo Nishikawa |
2008-12-23 |
| 7447725 |
Apparatus for controlling rounding modes in single instruction multiple data (SIMD) floating-point units |
Sang Hoo Dhong, Harm Peter Hofstee, Christian Jacobi, Silvia M. Mueller |
2008-11-04 |
| 7406589 |
Processor having efficient function estimate instructions |
Sang Hoo Dhong, Gordon Clyde Fossum, Harm Peter Hofstee, Brad W. Michael, Silvia M. Mueller |
2008-07-29 |
| 7392270 |
Apparatus and method for reducing the latency of sum-addressed shifters |
Sang Hoo Dhong, Christian Jacobi, Silvia M. Mueller, Hiroo Nishikawa |
2008-06-24 |
| 7290023 |
High performance implementation of exponent adjustment in a floating point design |
Sang Hoo Dhong, Silvia M. Mueller, Kevin D. Tran |
2007-10-30 |
| 7245159 |
Protecting one-hot logic against short-circuits during power-on |
Sang Hoo Dhong, Christian Jacobi, Silvia M. Mueller |
2007-07-17 |
| 7237163 |
Leakage current reduction system and method |
Sang Hoo Dhong, Silvia M. Mueller, Joel A. Silberman |
2007-06-26 |
| 7149877 |
Byte execution unit for carrying out byte instructions in a processor |
Sang Hoo Dhong, Brad W. Michael, Silvia M. Mueller, Kevin D. Tran |
2006-12-12 |
| 7137021 |
Power saving in FPU with gated power based on opcodes and data |
Sang Hoo Dhong, Silvia M. Mueller |
2006-11-14 |
| 7058830 |
Power saving in a floating point unit using a multiplier and aligner bypass |
Sang Hoo Dhong, Silvia M. Mueller, Kevin D. Tran |
2006-06-06 |
| 6914453 |
Integrated logic and latch design with clock gating at static input signals |
Sang Hoo Dhong, Joel A. Silberman, Naoka Yano |
2005-07-05 |
| 6829682 |
Destructive read architecture for dynamic random access memories |
Toshiaki Kirihata, Sang Hoo Dhong, Matthew R. Wordeman |
2004-12-07 |
| 6587388 |
Method and apparatus for reducing write operation time in dynamic random access memories |
Toshiaki Kirihata, Sang Hoo Dhong |
2003-07-01 |
| 6510093 |
Method and apparatus for cycle time reduction in a memory system using alternating reference cells and isolated sense lines |
Sang Hoo Dhong |
2003-01-21 |
| 5689621 |
Modular feedforward neural network architecture with learning |
Fathi M. Salam |
1997-11-18 |
