Issued Patents All Time
Showing 1–15 of 15 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12079484 | Random reads using multi-port memory and on-chip memory blocks | Abhishek Jain, Dinesh D. Gaitonde | 2024-09-03 |
| 11720255 | Random reads using multi-port memory and on-chip memory blocks | Abhishek Jain, Dinesh D. Gaitonde | 2023-08-08 |
| 11138019 | Routing in a compilation flow for a heterogeneous multi-core architecture | Akella Sastry, Rishi Surendran, Abnikant Singh | 2021-10-05 |
| 10747929 | Resolving timing violations in multi-die circuit designs | Dinesh D. Gaitonde, Chirag Ravishankar | 2020-08-18 |
| 10726181 | Regularity of fabrics in programmable logic devices | Martin L. Voogel, Trevor J. Bauer | 2020-07-28 |
| 10628547 | Routing circuit designs for implementation using a programmable network on chip | Ian A. Swarbrick, Dinesh D. Gaitonde | 2020-04-21 |
| 10614191 | Performing placement and routing concurrently | Dinesh D. Gaitonde | 2020-04-07 |
| 10503861 | Placing and routing an interface portion and a main portion of a circuit design | Dinesh D. Gaitonde, Sachin K. Bhutada, Aashish TRIPATHI, Ramakrishna K. Tanikella | 2019-12-10 |
| 10445456 | Incremental routing for circuit designs using a SAT router | — | 2019-10-15 |
| 10320386 | Programmable pipeline interface circuit | Ilya K. Ganusov, Brian C. Gaide | 2019-06-11 |
| 9954534 | Methods and circuits for preventing hold time violations | Ilya K. Ganusov, Benjamin S. Devlin | 2018-04-24 |
| 9935870 | Channel selection in multi-channel switching network | — | 2018-04-03 |
| 9882562 | Rotated integrated circuit die and chip packages having the same | Martin L. Voogel, Rafael C. Camarota | 2018-01-30 |
| 9875330 | Folding duplicate instances of modules in a circuit design | Ilya K. Ganusov, Ashish Sirasao, Alireza S. Kaviani | 2018-01-23 |
| 9235671 | Combining logic elements into pairs in a circuit design system | — | 2016-01-12 |