Issued Patents All Time
Showing 25 most recent of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12182261 | Controlling use of data determined by a resolve-pending speculative operation | Alastair David Reid, Albin Pierrick Tonnerre, Peter Richard Greenhalgh, Ian Michael Caulfield, Timothy Hayes +1 more | 2024-12-31 |
| 12099846 | Shared unit instruction execution | Cedric Denis Robert Airaud, Natalya Bondarenko, Luca MARONCELLI, Geoffray Matthieu Lacourba | 2024-09-24 |
| 11941403 | Selective prediction based on correlation between a given instruction and a subset of a set of monitored instructions ordinarily used to generate predictions for that given instruction | Houdhaifa BOUZGUARROU, Guillaume Bolbenes, Thibaut Elie Lanois | 2024-03-26 |
| 11803388 | Apparatus and method for predicting source operand values and optimized processing of instructions | Peter Richard Greenhalgh, Ian Michael Caulfield, Albin Pierrick Tonnerre | 2023-10-31 |
| 11580032 | Technique for training a prediction apparatus | Natalya Bondarenko, Cedric Denis Robert Airaud, Geoffray Matthieu Lacourba | 2023-02-14 |
| 11550620 | Task dispatch | Hakan Persson, Matthew Evans, Albin Pierrick Tonnerre | 2023-01-10 |
| 11526615 | Speculative side-channel hint instruction | Peter Richard Greenhalgh, Ian Michael Caulfield, Albin Pierrick Tonnerre | 2022-12-13 |
| 11403105 | Detecting misprediction when an additional branch direction prediction determined using value prediction is considered more accurate than an initial branch direction prediction | Vladimir Vasekin, David Michael Bull, Alexei Fedorov | 2022-08-02 |
| 11397584 | Tracking speculative data caching | Ian Michael Caulfield, Peter Richard Greenhalgh, Albin Pierrick Tonnerre | 2022-07-26 |
| 11392383 | Apparatus and method for prefetching data items | Ian Michael Caulfield, Peter Richard Greenhalgh, Albin Pierrick Tonnerre | 2022-07-19 |
| 11340901 | Apparatus and method for controlling allocation of instructions into an instruction cache storage | Peter Richard Greenhalgh, Ian Michael Caulfield, Albin Pierrick Tonnerre | 2022-05-24 |
| 11263133 | Cache control in presence of speculative read operations | Andreas Lars Sandberg, Stephan Diestelhorst, Nikos NIKOLERIS, Ian Michael Caulfield, Peter Richard Greenhalgh +1 more | 2022-03-01 |
| 11263014 | Sharing instruction encoding space between a coprocessor and auxiliary execution circuitry | Thomas Christoper Grocutt, Simon John Craske, Carlo Dario Fanara, Jean Sébastien Leroy | 2022-03-01 |
| 11126714 | Encoding of input to storage circuitry | Alastair David Reid, Dominic Phillip MULLIGAN, Milosch Meriac, Matthias Lothar Boettcher, Nathan Yong Seng Chong +5 more | 2021-09-21 |
| 10831499 | Apparatus and method for performing branch prediction | Houdhaifa BOUZGUARROU, Guillaume Bolbenes, Albin Pierrick Tonnerre | 2020-11-10 |
| 10613869 | Branch target address provision | Peter Richard Greenhalgh, Jose Gonzalez-Gonzalez | 2020-04-07 |
| 10394716 | Apparatus and method for controlling allocation of data into a cache storage | Peter Richard Greenhalgh, Ian Michael Caulfield, Albin Pierrick Tonnerre, Jeffrey Kehl | 2019-08-27 |
| 9424045 | Data processing apparatus and method for controlling use of an issue queue to represent an instruction suitable for execution by a wide operand execution unit | Cedric Denis Robert Airaud, Luca Scalabrino, Frederic Jean Denis Arsanto, Guillaume Schon, Albin Pierick Tonnerre | 2016-08-23 |
| 9361112 | Return address prediction | Clément Marc Demongeot, Louis-Marie Vincent Mouton, Jocelyn Francois Orion Jaubert, Albin Pierick Tonnerre | 2016-06-07 |
| 9311088 | Apparatus and method for mapping architectural registers to physical registers | Louis-Marie Vincent Mouton, Luca Scalabrino, Richard Roy Grisenthwaite, David Hennah Mansell | 2016-04-12 |
| 9223701 | Data processing apparatus and method for performing load-exclusive and store-exclusive operations | Philippe Jean-Pierre Raphalen, Melanie Emanuelle Lucie Teyssier, Albin Pierick Tonnerre | 2015-12-29 |
| 9075621 | Error recovery upon reaching oldest instruction marked with error or upon timed expiration by flushing instructions in pipeline pending queue and restarting execution | Guillaume Schon, Melanie Emanuelle Lucie Teyssier, Luca Scalabrino, David Michael Bull | 2015-07-07 |
| 9052909 | Recovering from exceptions and timing errors | Luca Scalabrino, Guillaume Schon, Melanie Emanuelle Lucie Teyssier | 2015-06-09 |
| 8738971 | Limiting certain processing activities as error rate probability rises | Luca Scalabrino, David Michael Bull | 2014-05-27 |
| 8706965 | Apparatus and method for handling access operations issued to local cache structures within a data processing apparatus | Louis-Marie Vincent Mouton, Luca Scalabrino | 2014-04-22 |