Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7810060 | Critical area computation of composite fault mechanisms using Voronoi diagrams | Robert J. Allen, Mervyn Y. Tan | 2010-10-05 |
| 7752580 | Method and system for analyzing an integrated circuit based on sample windows selected using an open deterministic sequencing technique | Sarah C. Braasch, Jason D. Hibbeler, Rouwaida N. Kanj, Daniel N. Maynard, Sani R. Nassif | 2010-07-06 |
| 7752589 | Method, apparatus, and computer program product for displaying and modifying the critical area of an integrated circuit design | Robert J. Allen, Sarah C. Braasch, Matthew T. Guzowski, Jason D. Hibbeler, Daniel N. Maynard +3 more | 2010-07-06 |
| 7703061 | IC design modeling allowing dimension-dependent rule checking | Daniel N. Maynard | 2010-04-20 |
| 7685553 | System and method for global circuit routing incorporating estimation of critical area estimate metrics | Ruchir Puri, Mervyn Y. Tan, Louise H. Trevillyan, Hua Xiang | 2010-03-23 |
| 7661080 | Method and apparatus for net-aware critical area extraction | Sarah C. Braasch, Mervyn Y. Tan | 2010-02-09 |
| 7577927 | IC design modeling allowing dimension-dependent rule checking | Daniel N. Maynard | 2009-08-18 |
| 7555735 | IC design modeling allowing dimension-dependent rule checking | Daniel N. Maynard | 2009-06-30 |
| 7404159 | Critical area computation of composite fault mechanisms using Voronoi diagrams | Robert J. Allen, Mervyn Y. Tan | 2008-07-22 |
| 7404164 | IC design modeling allowing dimension-dependent rule checking | Daniel N. Maynard | 2008-07-22 |
| 7240306 | Integrated circuit layout critical area determination using Voronoi diagrams and shape biasing | Robert J. Allen, Peter Chan, Sarah C. Prue, Mervyn Y. Tan | 2007-07-03 |
| 7143371 | Critical area computation of composite fault mechanisms using voronoi diagrams | Robert J. Allen, Mervyn Y. Tan | 2006-11-28 |
| 6317859 | Method and system for determining critical area for circuit layouts | — | 2001-11-13 |
| 6247853 | Incremental method for critical area and critical region computation of via blocks | Mark A. Lavin, Gustavo E. Tellez, Archibald J. Allen | 2001-06-19 |
| 6178539 | Method and system for determining critical area for circuit layouts using voronoi diagrams | Der-Tsai Lee | 2001-01-23 |
| 6044208 | Incremental critical area computation for VLSI yield prediction | Mark A. Lavin | 2000-03-28 |