Issued Patents All Time
Showing 25 most recent of 87 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10965442 | Low-power, low-latency time-to-digital-converter-based serial link | Bupesh Pandita, Jon Boyette, Hadi Goudarzi, Yong Suk Jun, Zhi Zhu +1 more | 2021-03-30 |
| 10637637 | Fixing dead-zone in clock data recovery circuits | Hadi Goudarzi, Jon Boyette, Julian Puscar | 2020-04-28 |
| 10476434 | Quadrature clock generation with injection locking | Bupesh Pandita, Zhuo Gao | 2019-11-12 |
| 10419204 | Serializer-deserializer with frequency doubler | Bupesh Pandita, Zhuo Gao | 2019-09-17 |
| 10389366 | SerDes with adaptive clock data recovery | Bupesh Pandita, Jon Boyette | 2019-08-20 |
| 10382190 | Optimizing clock/data recovery power while maintaining link stability in source synchronous applications | Rajeev Sharma, Santhosh Kumar Gude, Parth Arvindbhai Patel, Hadi Goudarzi | 2019-08-13 |
| 10355702 | Hybrid phase-locked loop | Zhuo Gao, Bupesh Pandita | 2019-07-16 |
| 10355701 | Apparatus and method for frequency calibration of voltage controlled oscillator (VCO) including determining VCO frequency range | Bupesh Pandita, Zhuo Gao | 2019-07-16 |
| 9998126 | Delay locked loop (DLL) employing pulse to digital converter (PDC) for calibration | Bupesh Pandita | 2018-06-12 |
| 9971312 | Pulse to digital converter | Bupesh Pandita | 2018-05-15 |
| 9755817 | Compact phase interpolator | Hanan Cohen, Li Sun, Zhiqin Chen | 2017-09-05 |
| 9602317 | Apparatus and method for combining currents from passive equalizer in sense amplifier | Hanan Cohen, Bupesh Pandita | 2017-03-21 |
| 9577646 | Fractional phase locked loop (PLL) architecture | Bupesh Pandita, Hanan Cohen, Kenneth Luis Arcudia | 2017-02-21 |
| 8736304 | Self-biased high speed level shifter circuit | David William Boerstler, Kazuhiko Miki, Jieming Qi | 2014-05-27 |
| 8381143 | Structure for a duty cycle correction circuit | David William Boerstler, Jieming Qi | 2013-02-19 |
| 8108813 | Structure for a circuit obtaining desired phase locked loop duty cycle without pre-scaler | David William Boerstler, Masaaki Kaneko, Jieming Qi | 2012-01-31 |
| 8086989 | Structure for glitchless clock multiplexer optimized for synchronous and asynchronous clocks | Takeo Yasuda | 2011-12-27 |
| 8054119 | System and method for on/off-chip characterization of pulse-width limiter outputs | David William Boerstler, Jieming Qi | 2011-11-08 |
| 8041537 | Clock duty cycle measurement with charge pump without using reference clock calibration | Jieming Qi, David William Boerstler, Masaaki Kaneko | 2011-10-18 |
| 8037431 | Structure for interleaved voltage controlled oscillator | David William Boerstler, Jieming Qi, Mike Shen | 2011-10-11 |
| 8032850 | Structure for an absolute duty cycle measurement circuit | David William Boerstler, Masaaki Kaneko, Jieming Qi, Bin Wan | 2011-10-04 |
| 7994830 | Systems and methods for PLL linearity measurement, PLL output duty cycle measurement and duty cycle correction | Masaaki Kaneko, David William Boerstler, Jieming Qi | 2011-08-09 |
| 7969250 | Structure for a programmable interpolative voltage controlled oscillator with adjustable range | David William Boerstler, Masaaki Kaneko, Jieming Qi | 2011-06-28 |
| 7958469 | Design structure for a phase locked loop with stabilized dynamic response | David William Boerstler, Jieming Qi | 2011-06-07 |
| 7917795 | Digital circuit to measure and/or correct duty cycles | David William Boerstler, Byron L. Krauter, Kazuhiko Miki, Jieming Qi | 2011-03-29 |