Issued Patents All Time
Showing 1–25 of 54 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11500019 | Area-aware test pattern coverage optimization | — | 2022-11-15 |
| 11204384 | Methods and systems for switchable logic to recover integrated circuits with short circuits | — | 2021-12-21 |
| 9973191 | Power saving with dual-rail supply voltage scheme | — | 2018-05-15 |
| 9503086 | Lockup latch for subthreshold operation | — | 2016-11-22 |
| 8947070 | Apparatus and method for testing driver writeability strength on an integrated circuit | Ashish R. Jain | 2015-02-03 |
| 8712752 | IR(voltage) drop analysis in integrated circuit timing | Betty LAU, Anup S. Mehta | 2014-04-29 |
| 8650527 | Method and software tool for analyzing and reducing the failure rate of an integrated circuit | Antonietta Oliva, Gregory S. Scott, Vincent R. von Kaenel | 2014-02-11 |
| 8635503 | Scan latch with phase-free scan enable | Bo Tang | 2014-01-21 |
| 8533645 | Reducing narrow gate width effects in an integrated circuit design | — | 2013-09-10 |
| 8397199 | Versatile method and tool for simulation of aged transistors | Apurva H. Soni, Antonietta Oliva, Matthew Page, James E. Burnette, II | 2013-03-12 |
| 8341578 | Clock gater with test features and low setup time | Brian J. Campbell, Shaishav Desai, Pradeep Trivedi, Sridhar Narayanan | 2012-12-25 |
| 8332698 | Scan latch with phase-free scan enable | Bo Tang | 2012-12-11 |
| 8327310 | Method and software tool for analyzing and reducing the failure rate of an integrated circuit | Antonietta Oliva, Gregory S. Scott, Vincent R. von Kaenel | 2012-12-04 |
| 8305125 | Low latency synchronizer circuit | Bo Tang | 2012-11-06 |
| 8301943 | Pulse flop with enhanced scan implementation | Ashish R. Jain | 2012-10-30 |
| 8154275 | Apparatus and method for testing sense amplifier thresholds on an integrated circuit | Ashish R. Jain | 2012-04-10 |
| 8134387 | Self-gating synchronizer | Bo Tang | 2012-03-13 |
| 8125211 | Apparatus and method for testing driver writeability strength on an integrated circuit | Ashish R. Jain | 2012-02-28 |
| 8027213 | Mechanism for measuring read current variability of SRAM cells | Ashish R. Jain, Priya Ananthanarayanan, Greg M. Hess | 2011-09-27 |
| 7977998 | Apparatus and method for testing level shifter voltage thresholds on an integrated circuit | Ashish R. Jain, Priya Ananthanarayanan | 2011-07-12 |
| 7977976 | Self-gating synchronizer | Bo Tang | 2011-07-12 |
| 7843244 | Low latency synchronizer circuit | Bo Tang | 2010-11-30 |
| 7779372 | Clock gater with test features and low setup time | Brian J. Campbell, Shaishav Desai, Pradeep Trivedi, Sridhar Narayanan | 2010-08-17 |
| 7461305 | System and method for detecting and preventing race condition in circuits | Peter Smeys | 2008-12-02 |
| 7454674 | Digital jitter detector | Greg M. Hess, Andrew J. Demas, Ashish R. Jain | 2008-11-18 |