| 11495568 |
IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures |
Jayprakash Chipalkatti, Zuhair Bokharey, Brian Schieck, Julie Lam, Prashant Pathak |
2022-11-08 |
| 10957651 |
Package level power gating |
Luke Y. Chang, Narayan Kulshrestha |
2021-03-23 |
| 10943882 |
IC package design and methodology to compensate for die-substrate CTE mismatch at reflow temperatures |
Jayprakash Chipalkatti, Zuhair Bokharey, Brian Schieck, Julie Lam, Prashant Pathak |
2021-03-09 |
| 10685925 |
Resistance and capacitance balancing systems and methods |
Jim Dobbins, Sheetal Jain, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran |
2020-06-16 |
| 10600730 |
Cross talk reduction differential cross over routing systems and methods |
Jim Dobbins, Sheetal Jain, Yaping Zhou, Wenjun Shi, Sunil Sudhakaran |
2020-03-24 |