Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10120800 | History based memory speculation for partitioned cache memories | Ramaswamy Sivaramakrishnan, Serena Leung | 2018-11-06 |
| 10007629 | Inter-processor bus link and switch chip failure recovery | Thomas M. Wicki, Sumti Jairath, Kathirgamar Aingaran, Ali Vahidsafa, Paul N. Loewenstein | 2018-06-26 |
| 9892039 | Non-temporal write combining using cache resources | Mark Luttrell, Ramaswamy Sivaramakrishnan, Serena Leung | 2018-02-13 |
| 9836326 | Cache probe request to optimize I/O directed caching | Kathirgamar Aingaran, Sumti Jairath, Manling Yang, Serena Leung, Paul N. Loewenstein | 2017-12-05 |
| 9734071 | Method and apparatus for history-based snooping of last level caches | Serena Leung, Ramaswamy Sivaramakrishnan, Joann Lam | 2017-08-15 |
| 9571408 | Dynamic flow control using credit sharing | Kathirgamar Aingaran, Manling Yang | 2017-02-14 |
| 9460013 | Method and system for removal of a cache agent | Ali Vahidsafa, Venkatram Krishnaswamy, Thirumalai Swamy Suresh | 2016-10-04 |
| 8972663 | Broadcast cache coherence on partially-ordered network | Paul N. Loewenstein, Stephen E. Phillips, Connie W. Cheung, Serena Leung, Damien Walker +1 more | 2015-03-03 |
| 8904223 | Communication between domains of a processor operating on different clock signals | Manling Yang | 2014-12-02 |
| 5757686 | Method of decoupling the high order portion of the addend from the multiply result in an FMAC | Samuel D. Naffziger | 1998-05-26 |
| 5740087 | Apparatus and method for regulating power consumption in a digital system | Craig A. Heikes, Robert H. Miller | 1998-04-14 |
| 5740181 | Method and apparatus for at speed observability of pipelined circuits | Craig A. Heikes, Glenn T. Colon-Bonet, Robert H. Miller | 1998-04-14 |