| 6418496 |
System and apparatus including lowest priority logic to select a processor to receive an interrupt message |
Stephen S. Pawlowski |
2002-07-09 |
| 6263397 |
Mechanism for delivering interrupt messages |
William S. Wu, Mani Azimi, Stephen S. Pawlowski, M. Jayakumar |
2001-07-17 |
| 6219741 |
Transactions supporting interrupt destination redirection and level triggered interrupt semantics |
Stephen S. Pawlowski, Kimberly C. Weier |
2001-04-17 |
| 5958037 |
Apparatus and method for identifying the features and the origin of a computer microprocessor |
Robert S. Dreyer, William M. Corwin, Donald B. Alpert, Tsu-Hua Wang, Frederick J. Pollack |
1999-09-28 |
| 5848279 |
Mechanism for delivering interrupt messages |
William S. Wu, Mani Azimi, Stephen S. Pawlowski, Muthurajan Jayakumar |
1998-12-08 |
| 5794066 |
Apparatus and method for identifying the features and the origin of a computer microprocessor |
Robert S. Dreyer, William M. Corwin, Tsu-Hua Wang, Frederick J. Pollack |
1998-08-11 |