Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8392663 | Coherent instruction cache utilizing cache-op execution resources | Ryan C. Kinter, Matthias Knoth | 2013-03-05 |
| 8234456 | Apparatus and method for controlling the exclusivity mode of a level-two cache | Jinwoo Kim | 2012-07-31 |
| 8151268 | Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency | Ryan C. Kinter, Michael Gottlieb Jensen, Sanjay Vishin | 2012-04-03 |
| 7917699 | Apparatus and method for controlling the exclusivity mode of a level-two cache | Jinwoo Kim | 2011-03-29 |
| 7886129 | Configurable co-processor interface | Lawrence Henry Hudepohl, Radhika Thekkath, Franz Treue | 2011-02-08 |
| 7873810 | Microprocessor instruction using address index values to enable access of a virtual buffer in circular fashion | Ryan C. Kinter, Radhika Thekkath, Chinh Tran | 2011-01-18 |
| 7853777 | Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions | Ryan C. Kinter, G. Michael Uhler, Sanjay Vishin | 2010-12-14 |
| 7752627 | Leaky-bucket thread scheduler in a multithreading microprocessor | Ryan C. Kinter, Thomas A. Petersen, Sanjay Vishin | 2010-07-06 |
| 7698533 | Configurable co-processor interface | Lawrence Henry Hudepohl, Radhika Thekkath, Franz Treue | 2010-04-13 |
| 7664936 | Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages | Michael Gottlieb Jensen, Ryan C. Kinter, Sanjay Vishin | 2010-02-16 |
| 7657891 | Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency | Michael Gottlieb Jensen, Ryan C. Kinter, Sanjay Vishin | 2010-02-02 |
| 7627770 | Apparatus and method for automatic low power mode invocation in a multi-threaded processor | — | 2009-12-01 |
| 7613904 | Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler | Ryan C. Kinter, Kevin D. Kissell, Thomas A. Petersen | 2009-11-03 |
| 7600135 | Apparatus and method for software specified power management performance using low power virtual threads | — | 2009-10-06 |
| 7594089 | Smart memory based synchronization controller for a multi-threaded multiprocessor SoC | Sanjay Vishin, Kevin D. Kissell, Ryan C. Kinter | 2009-09-22 |
| 7424599 | Apparatus, method, and instruction for software management of multiple computational contexts in a multithreaded microprocessor | Kevin D. Kissell | 2008-09-09 |
| 7315937 | Microprocessor instructions for efficient bit stream extractions | Ryan C. Kinter, Rivka Shenhav, Radhika Thekkath | 2008-01-01 |
| 7287147 | Configurable co-processor interface | Lawrence Henry Hudepohl, Radhika Thekkath, Franz Treue | 2007-10-23 |
| 7237090 | Configurable out-of-order data transfer in a coprocessor interface | Lawrence Henry Hudepohl, Radhika Thekkath, Franz Treue | 2007-06-26 |
| 7194599 | Configurable co-processor interface | Lawrence Henry Hudepohl, Radhika Thekkath, Franz Treue | 2007-03-20 |
| 7168066 | Tracing out-of order load data | Radhika Thekkath, George Michael Uhler, Franz Treue, Lawrence Henry Hudepohl | 2007-01-23 |
| 6754804 | Coprocessor interface transferring multiple instructions simultaneously along with issue path designation and/or issue order designation for the instructions | Lawrence Henry Hudepohl, Radhika Thekkath, Franz Treue | 2004-06-22 |
| 6742165 | System, method and computer program product for web-based integrated circuit design | Lavi A. Lev, David A. Courtright, John Knowles | 2004-05-25 |
| 6233656 | Bandwidth optimization cache | Wei-Ting Lin | 2001-05-15 |
| 6163540 | System and method for establishing unique sequence identification in an information exchange of a system network | Cyrus C. Cheung | 2000-12-19 |