Issued Patents All Time
Showing 25 most recent of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10877755 | Processor load using a bit vector to calculate effective address | Erik Schlanger, Daniel Fowler | 2020-12-29 |
| 10216515 | Processor load using a bit vector to calculate effective address | Erik Schlanger, Daniel Fowler | 2019-02-26 |
| 7472259 | Multi-cycle instructions | Gregory A. Overkamp, Ravi P. Singh | 2008-12-30 |
| 7366876 | Efficient emulation instruction dispatch based on instruction width | Ravi P. Singh, Gregory A. Overkamp, Tien Dinh | 2008-04-29 |
| 7360059 | Variable width alignment engine for aligning instructions based on transition between buffers | Thomas Tomazin, William C. Anderson, Kayla Chalmers, Juan Guillermo Revilla, Ravi P. Singh | 2008-04-15 |
| 7272705 | Early exception detection | Juan Guillermo Revilla, Ravi P. Singh | 2007-09-18 |
| 7168032 | Data synchronization for a test access port | Ravi P. Singh, Ravi Kolagotla, Tien Dinh | 2007-01-23 |
| 7155570 | FIFO write/LIFO read trace buffer with software and hardware loop compression | Ravi P. Singh, Gregory A. Overkamp | 2006-12-26 |
| 7100033 | Controlling the timing of test modes in a multiple processor system | Minesh S. Desai, Gerold Mueller, Peter Lachner | 2006-08-29 |
| 7082516 | Aligning instructions using a variable width alignment engine having an intelligent buffer refill mechanism | Thomas Tomazin, William C. Anderson, Kayla Chalmers, Juan Guillermo Revilla, Ravi P. Singh | 2006-07-25 |
| 7069420 | Decode and dispatch of multi-issue and multiple width instructions | Gregory A. Overkamp, Ravi P. Singh | 2006-06-27 |
| 7065636 | Hardware loops and pipeline system using advanced generation of loop parameters | Ryo Inoue, Ravi P. Singh, Gregory A. Overkamp | 2006-06-20 |
| 7043582 | Self-nesting interrupts | Ravi P. Singh, Thomas Tomazin, Jose Fridman, Michael S. Allen | 2006-05-09 |
| 7036000 | Valid bit generation and tracking in a pipelined processor | Ravi P. Singh, Gregory A. Overkamp, Thomas Tomazin | 2006-04-25 |
| 7028165 | Processor stalling | Ravi P. Singh, Gregory A. Overkamp | 2006-04-11 |
| 6986026 | Single-step processing and selecting debugging modes | Ravi P. Singh, Tien Dingh, Ravi Kolagotla, Marc Hoffman, Russell L. Rivin | 2006-01-10 |
| 6976151 | Decoding an instruction portion and forwarding part of the portion to a first destination, re-encoding a different part of the portion and forwarding to a second destination | Gregory A. Overkamp, Ravi P. Singh | 2005-12-13 |
| 6948056 | Maintaining even and odd array pointers to extreme values by searching and comparing multiple elements concurrently where a pointer is adjusted after processing to account for a number of pipeline stages | Ravi Kolagotla, Jose Fridman | 2005-09-20 |
| 6920547 | Register adjustment based on adjustment values determined at multiple stages within a pipeline of a processor | Ravi P. Singh, Gregory A. Overkamp | 2005-07-19 |
| 6920515 | Early exception detection | Juan Guillermo Revilla, Ravi P. Singh | 2005-07-19 |
| 6898693 | Hardware loops | Ravi P. Singh, Gregory A. Overkamp | 2005-05-24 |
| 6842812 | Event handling | Ravi P. Singh, Gregory A. Overkamp | 2005-01-11 |
| 6829701 | Watchpoint engine for a pipelined processor | Ravi P. Singh, Gregory A. Overkamp | 2004-12-07 |
| 6823448 | Exception handling using an exception pipeline in a pipelined processor | Ravi P. Singh, Gregory A. Overkamp | 2004-11-23 |
| 6789184 | Instruction address generation and tracking in a pipelined processor | Ravi P. Singh, Gregory A. Overkamp | 2004-09-07 |