Issued Patents All Time
Showing 25 most recent of 28 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12229422 | On-chip atomic transaction engine | Rishabh Jain | 2025-02-18 |
| 12013807 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2024-06-18 |
| 11868628 | On-chip atomic transaction engine | Rishabh Jain | 2024-01-09 |
| 11360932 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2022-06-14 |
| 11334262 | On-chip atomic transaction engine | Rishabh Jain | 2022-05-17 |
| 10877755 | Processor load using a bit vector to calculate effective address | Charles P. Roth, Daniel Fowler | 2020-12-29 |
| 10732865 | Distributed shared memory using interconnected atomic transaction engines at respective memory interfaces | Rishabh Jain | 2020-08-04 |
| 10725947 | Bit vector gather row count calculation and handling in direct memory access engine | Rishabh Jain, David A. Brown, Michael Alexander Duller, Christopher Joseph Daniels | 2020-07-28 |
| 10614023 | Processor core to coprocessor interface with FIFO semantics | David A. Brown, Daniel Fowler, Rishabh Jain, Michael Alexander Duller | 2020-04-07 |
| 10606797 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2020-03-31 |
| 10599488 | Multi-purpose events for notification and sequence control in multi-core processor systems | David A. Brown, Rishabh Jain, Michael Alexander Duller | 2020-03-24 |
| 10579391 | System on a chip hardware block for translating commands from processor to read boot code from off-chip non-volatile memory device | Eric Devolder, Ashraf Ahmed | 2020-03-03 |
| 10521395 | Systems and methods for implementing an intelligence processing computing architecture | David Fick, Malav Parikh, Paul Toth, Adam Caughron, Vimal Reddy +5 more | 2019-12-31 |
| 10402425 | Tuple encoding aware direct memory access engine for scratchpad enabled multi-core processors | David A. Brown, Rishabh Jain, Michael Alexander Duller, Sam Idicula, David Joseph Hawkins +1 more | 2019-09-03 |
| 10380058 | Processor core to coprocessor interface with FIFO semantics | David A. Brown, Daniel Fowler, Rishabh Jain, Michael Alexander Duller | 2019-08-13 |
| 10216515 | Processor load using a bit vector to calculate effective address | Charles P. Roth, Daniel Fowler | 2019-02-26 |
| 10176114 | Row identification number generation in database direct memory access engine | David A. Brown, Sam Idicula, Rishabh Jain, Michael Alexander Duller | 2019-01-08 |
| 10061832 | Database tuple-encoding-aware data partitioning in a direct memory access engine | David A. Brown, Sam Idicula, Rishabh Jain, Michael Alexander Duller, Christopher Joseph Daniels +1 more | 2018-08-28 |
| 10061714 | Tuple encoding aware direct memory access engine for scratchpad enabled multicore processors | David A. Brown, Rishabh Jain, Michael Alexander Duller, Sam Idicula, David Joseph Hawkins | 2018-08-28 |
| 10055358 | Run length encoding aware direct memory access filtering engine for scratchpad enabled multicore processors | David A. Brown, Rishabh Jain, Sam Idicula, David Joseph Hawkins | 2018-08-21 |
| 9990282 | Address space expander for a processor | Joseph Wright, Eric Devolder | 2018-06-05 |
| 9557997 | Configurable logic constructs in a loop buffer | Aarti Basant, Brian Gold | 2017-01-31 |
| 8923384 | System, method and device for processing macroblock video data | Rens Ross | 2014-12-30 |
| 8576924 | Piecewise processing of overlap smoothing and in-loop deblocking | Bill K. C. Kwan, Casey King, Raquel Rozas | 2013-11-05 |
| 8462841 | System, method and device to encode and decode video data having multiple video data formats | Brendan D. Donahe, Eric Devolder, Rens Ross, Sandip Ladhani, Eric Swartzendruber | 2013-06-11 |