Issued Patents All Time
Showing 1–25 of 30 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12381167 | Semiconductor structure having vias with different dimensions | Shing-Yih Shih | 2025-08-05 |
| 12347730 | Method of manufacturing semiconductor structure having vias with different dimensions | Shing-Yih Shih | 2025-07-01 |
| 12159400 | System and method for real time assay monitoring | Yu-Heng Cheng, Setareh Duquette, Lisa A. Jones, Javier Andres Perez-Sepulveda | 2024-12-03 |
| 11854196 | System and method for real time assay monitoring | Yu-Heng Cheng, Setareh Duquette, Lisa A. Jones, Javier Andres Perez-Sepulveda | 2023-12-26 |
| 11450556 | Semiconductor structure | Shing-Yih Shih | 2022-09-20 |
| 11320348 | System and method for real time assay monitoring | Yu-Heng Cheng, Setareh Duquette, Lisa A. Jones, Javier Andres Perez-Sepulveda | 2022-05-03 |
| 11222080 | Guidance content automatic obtaining and displaying equipment | — | 2022-01-11 |
| 11183399 | Semiconductor device and method of manufacture | Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu +6 more | 2021-11-23 |
| 11101140 | Semiconductor device and method of manufacture | Wen-Hsin Wei, Hsien-Pin Hu, Shang-Yun Hou, Chi-Hsi Wu, Chen-Hua Yu +6 more | 2021-08-24 |
| 10811309 | Semiconductor structure and fabrication thereof | Shing-Yih Shih | 2020-10-20 |
| 10777522 | Semiconductor structure and method of manufacturing the same | — | 2020-09-15 |
| 10115594 | Method of forming fine island patterns of semiconductor devices | Shing-Yih Shih, Chiang-Lin Shih | 2018-10-30 |
| 10048742 | Integrated circuit and electronic device | Yi-Ping Kao, Chun-Sung Su | 2018-08-14 |
| 9188828 | Control circuit and method for maintaining light transmittance of electrochromic device | Yi-Wen Chung | 2015-11-17 |
| 8772928 | Integrated circuit chip with reduced IR drop | Ya-Ting Chang, Chia-Lin Chuang | 2014-07-08 |
| 8748217 | Metal-based solution treatment of CIGS absorber layer in thin-film solar cells | Yong-Ping Chan, Kai-Yu Tung, Cheng-Tao Lee | 2014-06-10 |
| 8642479 | Method for forming openings in semiconductor device | Yi-Nan Chen, Hsien-Wen Liu | 2014-02-04 |
| 8640074 | Digital circuit block having reducing supply voltage drop and method for constructing the same | Shen-Yu Huang | 2014-01-28 |
| 8592320 | Method for forming fin-shaped semiconductor structure | Yi-Nan Chen, Hsien-Wen Liu | 2013-11-26 |
| 8389402 | Method for via formation in a semiconductor device | Yi-Nan Chen, Hsien-Wen Liu | 2013-03-05 |
| 7949988 | Layout circuit having a combined tie cell | Tung-Kai Tsai | 2011-05-24 |
| 7678692 | Fabrication method for a damascene bit line contact plug | Yi-Nan Chen, Jeng-Ping Lin, Hui-Min Mao | 2010-03-16 |
| 7285377 | Fabrication method for a damascene bit line contact plug | Yi-Nan Chen, Jeng-Ping Lin, Hui-Min Mao | 2007-10-23 |
| 7067418 | Interconnect structure and method for fabricating the same | Tse-Yao Huang, Yi-Nan Chen | 2006-06-27 |
| 6992393 | Interconnect structure and method for fabricating the same | Tse-Yao Huang, Yi-Nan Chen | 2006-01-31 |