Issued Patents All Time
Showing 25 most recent of 219 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10134631 | Size-filtered multimetal structures | David V. Horak, Shom Ponoth, Chih-Chao Yang | 2018-11-20 |
| 10032773 | FinFET with reduced capacitance | Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz | 2018-07-24 |
| 9947763 | FinFET with reduced capacitance | Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz | 2018-04-17 |
| 9941385 | Finfet with reduced capacitance | Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz | 2018-04-10 |
| 9660030 | Replacement gate electrode with a self-aligned dielectric spacer | Shom Ponoth, Marc A. Bergendahl, Steven J. Holmes, David V. Horak, Chih-Chao Yang | 2017-05-23 |
| 9627377 | Self-aligned dielectric isolation for FinFET devices | Marc A. Bergendahl, Kangguo Cheng, David V. Horak, Ali Khakifirooz, Shom Ponoth +4 more | 2017-04-18 |
| 9620619 | Borderless contact structure | Veeraraghavan S. Basker, David V. Horak, Shom Ponoth, Chih-Chao Yang | 2017-04-11 |
| 9536979 | FinFET with reduced capacitance | Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz | 2017-01-03 |
| 9496356 | Under-spacer doping in fin-based semiconductor devices | Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz | 2016-11-15 |
| 9484254 | Size-filtered multimetal structures | David V. Horak, Shom Ponoth, Chih-Chao Yang | 2016-11-01 |
| 9455323 | Under-spacer doping in fin-based semiconductor devices | Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz | 2016-09-27 |
| 9379198 | Integrated circuit structure having selectively formed metal cap | Chih-Chao Yang, David V. Horak, Shom Ponoth | 2016-06-28 |
| 9368590 | Silicon-on-insulator transistor with self-aligned borderless source/drain contacts | Susan S. Fan, Balasubramanian S. Haran, David V. Horak | 2016-06-14 |
| 9312275 | FinFET with reduced capacitance | Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz | 2016-04-12 |
| 9269621 | Dual damascene dual alignment interconnect scheme | Steven J. Holmes, David V. Horak, Shom Ponoth, Chih-Chao Yang | 2016-02-23 |
| 9263388 | Overlay-tolerant via mask and reactive ion etch (RIE) technique | Steven J. Holmes, David V. Horak, Shom Ponoth, Chih-Chao Yang | 2016-02-16 |
| 9263290 | Sub-lithographic semiconductor structures with non-constant pitch | Marc A. Bergendahl, David V. Horak, Shom Ponoth, Chih-Chao Yang | 2016-02-16 |
| 9202879 | Mask free protection of work function material portions in wide replacement gate electrodes | Marc A. Bergendahl, David V. Horak, Shom Ponoth, Chih-Chao Yang | 2015-12-01 |
| 9196613 | Stress inducing contact metal in FinFET CMOS | Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz | 2015-11-24 |
| 9177820 | Sub-lithographic semiconductor structures with non-constant pitch | Marc A. Bergendahl, David V. Horak, Shom Ponoth, Chih-Chao Yang | 2015-11-03 |
| 9141749 | Interconnect structures and methods for back end of the line integration | David V. Horak, Shom Ponoth, Chih-Chao Yang | 2015-09-22 |
| 9105641 | Profile control in interconnect structures | Shyng-Tsong Chen, Samuel S. Choi, Steven J. Holmes, David V. Horak, Wai-Kin Li +4 more | 2015-08-11 |
| 9059254 | Overlay-tolerant via mask and reactive ion etch (RIE) technique | Steven J. Holmes, David V. Horak, Shom Ponoth, Chih-Chao Yang | 2015-06-16 |
| 9040363 | FinFET with reduced capacitance | Veeraraghavan S. Basker, Kangguo Cheng, Ali Khakifirooz | 2015-05-26 |
| 8946908 | Dual-metal self-aligned wires and vias | Steven J. Holmes, David V. Horak, Shom Ponoth, Chih-Chao Yang | 2015-02-03 |