Issued Patents All Time
Showing 25 most recent of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9496877 | Pseudo-inverter circuit with multiple independent gate transistors | Richard Ferrant, Bich-Yen Nguyen | 2016-11-15 |
| 9490264 | Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device | Richard Ferrant | 2016-11-08 |
| 9159400 | Semiconductor memory having staggered sense amplifiers associated with a local column decoder | Richard Ferrant, Gerhard Enders | 2015-10-13 |
| 9035474 | Method for manufacturing a semiconductor substrate | Richard Ferrant, Konstantin Bourdelle, Bich-Yen Nguyen | 2015-05-19 |
| 8987114 | Bonded semiconductor structures and method of forming same | Bich-Yen Nguyen, Mariam Sadaka | 2015-03-24 |
| 8735946 | Substrate having a charged zone in an insulating buried layer | Mohamad A. Shaheen, Frédéric Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru +1 more | 2014-05-27 |
| 8664712 | Flash memory cell on SeOI having a second control gate buried under the insulating layer | Richard Ferrant | 2014-03-04 |
| 8652887 | Multi-layer structures and process for fabricating semiconductor devices | Bich-Yen Nguyen, Richard Ferrant | 2014-02-18 |
| 8654602 | Pseudo-inverter circuit on SeOI | Richard Ferrant, Bich-Yen Nguyen | 2014-02-18 |
| 8625374 | Nano-sense amplifier | Richard Ferrant, Bich-Yen Nguyen | 2014-01-07 |
| 8603896 | Method for transferring a monocrystalline semiconductor layer onto a support substrate | Gweltaz Gaudin | 2013-12-10 |
| 8575697 | SRAM-type memory cell | Richard Ferrant, Bich-Yen Nguyen | 2013-11-05 |
| 8535996 | Substrate having a charged zone in an insulating buried layer | Mohamad A. Shaheen, Frédéric Allibert, Gweltaz Gaudin, Fabrice Lallement, Didier Landru +1 more | 2013-09-17 |
| 8508289 | Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer | Richard Ferrant | 2013-08-13 |
| 8492844 | Fully depleted SOI device with buried doped layer | Gerhard Enders, Wolfgang Hoenlein, Franz Hofmann | 2013-07-23 |
| 8481408 | Relaxation of strained layers | Fabrice Letertre, Michael R. Krames, Melvin McLaurin, Nathan Gardner | 2013-07-09 |
| 8455938 | Device comprising a field-effect transistor in a silicon-on-insulator | Bich-Yen Nguyen, Richard Ferrant | 2013-06-04 |
| 8432216 | Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer | Richard Ferrant | 2013-04-30 |
| 8384425 | Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate | Richard Ferrant | 2013-02-26 |
| 8358552 | Nano-sense amplifier | Richard Ferrant, Bich-Yen Nguyen | 2013-01-22 |
| 8325506 | Devices and methods for comparing data in a content-addressable memory | Richard Ferrant | 2012-12-04 |
| 8309426 | Methods for manufacturing multilayer wafers with trench structures | Konstantin Bourdelle | 2012-11-13 |
| 8305803 | DRAM memory cell having a vertical bipolar injector | Richard Ferrant | 2012-11-06 |
| 8304833 | Memory cell with a channel buried beneath a dielectric layer | Richard Ferrant | 2012-11-06 |
| 8241942 | Method of fabricating a back-illuminated image sensor | Konstantin Bourdelle | 2012-08-14 |