Issued Patents All Time
Showing 1–7 of 7 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8886979 | Methods and apparatuses for reducing step loads of processors | Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Steve Undy | 2014-11-11 |
| 8479029 | Methods and apparatuses for reducing step loads of processors | Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Steve Undy | 2013-07-02 |
| 7992017 | Methods and apparatuses for reducing step loads of processors | Kevin Safford, Rohit Bhatia, Chris Bostak, Richard Blumberg, Steve Undy | 2011-08-02 |
| 7133319 | Programmable weak write test mode (PWWTM) bias generation having logic high output default mode | John Wuu, Donald R. Weiss | 2006-11-07 |
| 6728823 | Cache connection with bypassing feature | Shawn Walker, Terry L Lyon | 2004-04-27 |
| 6185148 | General purpose decode implementation for multiported memory array circuits | — | 2001-02-06 |
| 5740000 | ESD protection system for an integrated circuit with multiple power supply networks | Gordon W. Motley | 1998-04-14 |