Issued Patents All Time
Showing 1–25 of 90 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12306216 | Dynamic voltage regulator sensing for chiplet-based designs | Vikrant Thigle, Vijay Anand Mathiyalagan, Arun Chandrasekhar, Gerald Pasdast | 2025-05-20 |
| 11743058 | NVDIMM security with physically unclonable functions | Janani Swaminathan, Trinadhachari Kosuru, Santosh Balasubramanian | 2023-08-29 |
| 11307796 | Mapping memory allocation requests using various memory attributes | Anshuman Khandual, Saravanan Sethuraman, Venkata K. Tavva | 2022-04-19 |
| 11221905 | System to monitor computing hardware in a computing infrastructure facility | Vidhya Shankar Venkatesan, Diyanesh Babu C. Vidyapoornachary, Arun Joseph | 2022-01-11 |
| 11183140 | Human relationship-aware augmented display | Diwesh Pandey, Arun Joseph | 2021-11-23 |
| 10996074 | Activity recommendation based on a real-time mapping between activity characteristics and autonomous vehicle dynamics | Diwesh Pandey, Shiladitya Ghosh, Shashidhar Reddy, Arun Joseph | 2021-05-04 |
| 10891056 | Virtualization of memory compute functionality | Edgar R. Cordero, Arun Joseph, Diyanesh B. Vidyapoornachary | 2021-01-12 |
| 10884055 | Leakage power characterization at high temperatures for an integrated circuit | Diyanesh B. Chinnakkonda Vidyapoornachary, Arun Joseph, Charles R. Lefurgy, Spandana V. Rachamalla | 2021-01-05 |
| 10354028 | Formal verification driven power modeling and design verification | Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao | 2019-07-16 |
| 10031180 | Leakage power characterization at high temperatures for an integrated circuit | Diyanesh B. Chinnakkonda Vidyapoornachary, Arun Joseph, Charles R. Lefurgy, Spandana V. Rachamalla | 2018-07-24 |
| 9703563 | Detecting cross-talk on processor links | Robert W. Berry, Jr., Prasanna Jayaraman | 2017-07-11 |
| 9697306 | Formal verification driven power modeling and design verification | Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao | 2017-07-04 |
| 9684465 | Memory power management and data consolidation | Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Arun Joseph | 2017-06-20 |
| 9671840 | Multiple level computer system for temperature management for cooling fan control | Prasanna Jayaraman, Tony E. Sawan | 2017-06-06 |
| 9665154 | Subsystem-level power management in a multi-node virtual machine environment | Prasanna Jayaraman, Tony E. Sawan | 2017-05-30 |
| 9606741 | Memory power management and data consolidation | Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Arun Joseph | 2017-03-28 |
| 9558139 | System interconnect dynamic scaling handshake using spare bit-lane | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman | 2017-01-31 |
| 9552319 | System interconnect dynamic scaling handshake using spare bit-lane | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman | 2017-01-24 |
| 9541971 | Multiple level computer system temperature management for cooling fan control | Prasanna Jayaraman, Tony E. Sawan | 2017-01-10 |
| 9529406 | System interconnect dynamic scaling by lane width and operating frequency balancing | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman | 2016-12-27 |
| 9524013 | System interconnect dynamic scaling by lane width and operating frequency balancing | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman | 2016-12-20 |
| 9471239 | Memory power management and data consolidation | Diyanesh B. Chinnakkonda Vidyapoornachary, Edgar R. Cordero, Arun Joseph | 2016-10-18 |
| 9471540 | Detecting TSV defects in 3D packaging | Edgar R. Cordero, Girisankar Paulraj, Diyanesh B. Vidyapoornachary | 2016-10-18 |
| 9460251 | Formal verification driven power modeling and design verification | Arun Joseph, Pradeep Kumar Nalla, Rahul M. Rao | 2016-10-04 |
| 9459982 | Bus interface optimization by selecting bit-lanes having best performance margins | Daniel M. Dreps, Frank D. Ferraiolo, Prasanna Jayaraman | 2016-10-04 |