Issued Patents All Time
Showing 1–24 of 24 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12386506 | Tagged memory operated at lower VMIN in error tolerant system | Nitin Chawla, Giuseppe Desoli, Thomas Boesch, Surinder Singh, Manuj AYODHYAWASI | 2025-08-12 |
| 12292780 | Computing system power management device, system and method | Nitin Chawla, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch, Promod Kumar | 2025-05-06 |
| 12243584 | In-memory compute array with integrated bias elements | Tanmoy Roy, Nitin Chawla | 2025-03-04 |
| 11836346 | Tagged memory operated at lower vmin in error tolerant system | Nitin Chawla, Giuseppe Desoli, Thomas Boesch, Surinder Singh, Manuj AYODHYAWASI | 2023-12-05 |
| 11829730 | Elements for in-memory compute | Nitin Chawla, Tanmoy Roy, Giuseppe Desoli | 2023-11-28 |
| 11823771 | Streaming access memory device, system and method | Nitin Chawla, Thomas Boesch, Surinder Singh, Giuseppe Desoli | 2023-11-21 |
| 11798615 | High density array, in memory computing | Tanmoy Roy | 2023-10-24 |
| 11776650 | Memory calibration device, system and method | Tanmoy Roy | 2023-10-03 |
| 11749343 | Memory management device, system and method | Nitin Chawla, Tanmoy Roy | 2023-09-05 |
| 11726543 | Computing system power management device, system and method | Nitin Chawla, Giuseppe Desoli, Kedar Janardan Dhori, Thomas Boesch, Promod Kumar | 2023-08-15 |
| 11605424 | In-memory compute array with integrated bias elements | Tanmoy Roy, Nitin Chawla | 2023-03-14 |
| 11474788 | Elements for in-memory compute | Nitin Chawla, Tanmoy Roy, Giuseppe Desoli | 2022-10-18 |
| 11398289 | Memory calibration device, system and method | Tanmoy Roy | 2022-07-26 |
| 11360667 | Tagged memory operated at lower vmin in error tolerant system | Nitin Chawla, Giuseppe Desoli, Thomas Boesch, Surinder Singh, Manuj AYODHYAWASI | 2022-06-14 |
| 11335397 | High-density array, in memory computing | Tanmoy Roy | 2022-05-17 |
| 11257543 | Memory management device, system and method | Nitin Chawla, Tanmoy Roy | 2022-02-22 |
| 11094376 | In-memory compute array with integrated bias elements | Tanmoy Roy, Nitin Chawla | 2021-08-17 |
| 10637447 | Low voltage, master-slave flip-flop | Alok Tripathi, Amit Verma, Deepak Kumar Bihani, Tanmoy Roy, Tanuj Agrawal | 2020-04-28 |
| 10277207 | Low voltage, master-slave flip-flop | Alok Tripathi, Amit Verma, Deepak Kumar Bihani, Tanmoy Roy, Tanuj Agrawal | 2019-04-30 |
| 9305633 | SRAM cell and cell layout method | Gangaikondan Subramani Visweswaran | 2016-04-05 |
| 9177637 | Wide voltage range high performance sense amplifier | Gangaikondan Subramani Visweswaran | 2015-11-03 |
| 8982651 | Memory with an assist determination controller and associated methods | Gangaikondan Subramani Visweswaran | 2015-03-17 |
| 8724374 | Data-dependent pullup transistor supply and body bias voltage application for a static random access memory (SRAM) cell | Gangaikondan Subramani Visweswaran | 2014-05-13 |
| 8654570 | Low voltage write time enhanced SRAM cell and circuit extensions | Gangaikondan Subramani Visweswaran | 2014-02-18 |