Issued Patents All Time
Showing 1–20 of 20 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417023 | Host device caching of flash memory address mappings | Pratibind Kumar JHA, Manish Garg, Prakhar Srivastava, Santhosh Reddy AKAVARAM, Hung Vuong +1 more | 2025-09-16 |
| 11829662 | Image rendering based on location identifiers | Manohar Lal Kalwani | 2023-11-28 |
| 11790591 | Graphics processor health predictions | Manohar Lal Kalwani | 2023-10-17 |
| 11569799 | True single-phase clock (TSPC) NAND-based reset flip-flop | Aroma Bhat, Arani Roy, Mitesh Goyal | 2023-01-31 |
| 11366161 | True single phase clock (TSPC) pre-charge based flip-flop | Arani Roy, Arava Prakash, Aroma Bhat, Mitesh Goyal | 2022-06-21 |
| 11362648 | Pre-discharging based flip-flop with a negative setup time | Aroma Bhat, Abdur Rakheeb, Arani Roy, Mitesh Goyal | 2022-06-14 |
| 11347569 | Event-based framework for distributed applications | Bo Kampmann, Gaurav Roy, Lennart Conrad, Andrew James Stach, Alexandros Kalomoiros | 2022-05-31 |
| 11271011 | Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) | Shyam Agarwal, Parvinder Kumar Rana | 2022-03-08 |
| 11152942 | Three-input exclusive NOR/OR gate using a CMOS circuit | Hareharan Nagarajan, Sajal Mittal | 2021-10-19 |
| 10812055 | Flip flop circuit | Sajal Mittal, Aroma Bhat, Hareharan Nagarajan, Rahul Kataria | 2020-10-20 |
| 10748932 | Method for high performance standard cell design techniques in FinFET based library using local layout effects (LLE) | Shyam Agarwal, Parvinder Kumar Rana | 2020-08-18 |
| 10733599 | Accessing digital wallet information using a point-of-sale device | Jan Rosen, Bharat Savani, Abhishikth Nandam, Surojit Bhaduri | 2020-08-04 |
| 10727861 | Excess loop delay estimation and correction | Chandrajit Debnath, Rishi Mathur, Anand Mohan Pappu | 2020-07-28 |
| 10715118 | Flip-flop with single pre-charge node | Shyam Agarwal, Sandeep B V, Shreyas Samraksh Jayaprakash, Parvinder Kumar Rana | 2020-07-14 |
| 10672756 | Area and power efficient circuits for high-density standard cell libraries | Sajal Mittal, Utkarsh GARG | 2020-06-02 |
| 10651850 | Low voltage tolerant ultra-low power edge triggered flip-flop for standard cell library | Sajal Mittal, Jaskaran Singh Bhatia, Rajeela Deshpande, Parvinder Kumar Rana, Nikhila C M +1 more | 2020-05-12 |
| 10615815 | High-linearity flash analog to digital converter | Rishi Mathur, Chandrajit Debnath, Anand Mohan Pappu | 2020-04-07 |
| 10566959 | Sense amplifier flip-flop and method for fixing setup time violations in an integrated circuit | Sajal Mittal, Parvinder Kumar Rana, Rajeela Deshpande | 2020-02-18 |
| 10187017 | Clocking scheme in nonlinear systems for distortion improvement | Prasun Kali Bhattacharyya, Prasenjit Bhowmik | 2019-01-22 |
| 10103172 | Method for high performance standard cell design techniques in finFET based library using local layout effects (LLE) | Shyam Agarwal, Parvinder Kumar Rana | 2018-10-16 |