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Jianjun Cao, Guangyuan Zhao, Yoganand Saripalli, Zhikai Tang |
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Alexander Lidow, Jianjun Cao, Johan Tjeerd Strydom, Alana Nakata, Guangyuan Zhao |
2020-03-24 |
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Semiconductor devices with back surface isolation |
Alexander Lidow, Jianjun Cao, Johan Tjeerd Strydom, Alana Nakata, Guangyuan Zhao |
2019-06-04 |
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Paul Bridger |
2018-03-06 |
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2017-12-05 |
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III-nitride power semiconductor with a field relaxation feature |
— |
2017-05-02 |
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Alexander Lidow, Jianjun Cao, Johan Tjeerd Strydom, Alana Nakata, Guang Yuan Zhao |
2017-03-28 |
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High performance III-nitride power device |
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2016-10-18 |
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GaN device with reduced output capacitance and process for making same |
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Method to fabricate self-aligned isolation in gallium nitride devices and integrated circuits |
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GaN transistors with polysilicon layers for creating additional components |
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Integrated circuit with matching threshold voltages and method for making same |
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Isolation structure in gallium nitride devices and integrated circuits |
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2015-10-27 |
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Process for manufacture of super lattice using alternating high and low temperature layers to block parasitic current path |
Paul Bridger |
2015-10-13 |
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III-nitride monolithic IC |
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2015-09-22 |
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Michael A. Briere, Paul Bridger |
2015-08-25 |
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III-nitride heterojunction device |
Paul Bridger |
2015-04-07 |
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Enhancement mode gallium nitride transistor with improved gate characteristics |
Alexander Lidow, Alana Nakata, Jianjun Cao, Guang Yuan Zhao |
2015-03-03 |
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III-nitride power device |
Zhi He, Jianjun Cao |
2015-02-10 |
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Method for fabricating a III-nitride semiconductor device |
Zhi He, Jianjun Cao |
2015-01-27 |
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