Issued Patents All Time
Showing 1–25 of 45 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12398045 | Device and method for preparing sulfite | Haitao Xu, Mingbo Li, Renyuan Chen, Dahua Liu, Junmin Li +1 more | 2025-08-26 |
| 11731874 | System and method for resource recycling of sulfur dioxide | Haitao Xu, Mingbo Li, Renyuan Chen, Dahua Liu, Zhenshan Wu +2 more | 2023-08-22 |
| 11637548 | Resilient storage circuits | Tracey DellaRova | 2023-04-25 |
| 11381226 | Resilient storage circuits | Tracey DellaRova | 2022-07-05 |
| 10483951 | Techniques for detecting and correcting errors on a ring oscillator | Nelson Joseph Gaspard | 2019-11-19 |
| 10242732 | Memory elements with soft-error-upset (SEU) immunity using parasitic components | Weimin Zhang, Nelson Joseph Gaspard | 2019-03-26 |
| 10204906 | Memory with single-event latchup prevention circuitry | Weimin Zhang | 2019-02-12 |
| 9859358 | On-die capacitor (ODC) structure | Kyung Suk Oh, Charu Sardana, Guang Chen | 2018-01-02 |
| 9774316 | Techniques for detecting and correcting errors on a ring oscillator | Nelson Joseph Gaspard | 2017-09-26 |
| 9768757 | Register circuitry with asynchronous system reset | Nelson Joseph Gaspard, Wen Wu | 2017-09-19 |
| 9582374 | Memory array with redundant bits and memory element voting circuits | — | 2017-02-28 |
| 9559699 | CMOS global interconnect using multi-voltage(or current)-levels | Weimin Zhang | 2017-01-31 |
| 9543382 | FinFET with improved SEU performance | Wen Wu, Jeffrey T. Watt | 2017-01-10 |
| 9519743 | Optimal stacked transistor placement to increase single event transient robustness | Nelson Joseph Gaspard | 2016-12-13 |
| 9520182 | Memory elements with relay devices | Lin-Shih Liu, Mark T. Chan, Irfan Rahim, Jeffrey T. Watt | 2016-12-13 |
| 9508720 | Low leakage FinFET | Weimin Zhang | 2016-11-29 |
| 9496268 | Integrated circuits with asymmetric and stacked transistors | Jun Liu, Shankar Sinha, Shih-Lin Lee, Jeffrey Tung, Albert Ratnakumar +5 more | 2016-11-15 |
| 9479173 | Transition accelerator circuitry | David Lewis | 2016-10-25 |
| 9455338 | Methods for fabricating PNP bipolar junction transistors | Albert Ratnakumar | 2016-09-27 |
| 9419076 | Bipolar junction transistor | Weimin Zhang | 2016-08-16 |
| 9385718 | Input-output buffer circuit with a gate bias generator | Jun Liu, Bonnie I. Wang, Jeffrey T. Watt | 2016-07-05 |
| 9370745 | Flue gas-treating method and apparatus for treating acidic tail gas by using ammonia process | Changxiang Xu, Jing Luo, Guoguang FU | 2016-06-21 |
| 9344067 | Dual interlocked cell (DICE) storage element with reduced charge sharing | Wen Wu | 2016-05-17 |
| 9293452 | ESD transistor and a method to design the ESD transistor | Nor Razman Md Zin | 2016-03-22 |
| 8995175 | Memory circuit with PMOS access transistors | Jun Liu, Irfan Rahim, Andy L. Lee | 2015-03-31 |