Issued Patents All Time
Showing 76–100 of 129 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9383966 | Number squaring computer-implemented method and apparatus | Vlad Krasnov | 2016-07-05 |
| 9355068 | Vector multiplication with operand base system conversion and re-conversion | Vlad Krasnov | 2016-05-31 |
| 9325498 | Performing AES encryption or decryption in multiple modes with a single instruction | Martin G. Dixon, Srinivas Chennupaty | 2016-04-26 |
| 9317719 | SM3 hash algorithm acceleration processors, methods, systems, and instructions | Vlad Krasnov | 2016-04-19 |
| 9276750 | Secure processing environment measurement and attestation | Vincent R. Scarlata, Carlos V. Rozas, Simon P. Johnson, Uday Savagaonkar, Rebekah M. Leslie-Hurd +6 more | 2016-03-01 |
| 9268564 | Vector and scalar based modular exponentiation | Vlad Krasnov | 2016-02-23 |
| 9230120 | Architecture and instruction set for implementing advanced encryption standard (AES) | Wajdi K. Feghali, Vinodh Gopal | 2016-01-05 |
| 9158902 | Software modification for partial secure memory processing | Moshe Maor | 2015-10-13 |
| 9076019 | Method and apparatus for memory encryption with integrity check and protection against replay attacks | Uday Savagaonkar, Francis X. McKeen, Carlos V. Rozas, David M. Durham, Jacob Doweck +4 more | 2015-07-07 |
| 9047082 | Instruction-set architecture for programmable Cyclic Redundancy Check (CRC) computations | Vinodh Gopal, Gilbert M. Wolrich, Wajdi K. Feghali, Kirk S. Yap, Bradley A. Burres | 2015-06-02 |
| 9043604 | Method and apparatus for key provisioning of hardware devices | Ernest Brickell, Jiangtao Li, Carlos V. Rozas, Daniel Nemiroff, Vincent R. Scarlata +2 more | 2015-05-26 |
| 8923510 | Method and apparatus for efficiently implementing the advanced encryption standard | Michael E. Kounavis, Ram Krishnamurthy, Sanu K. Mathew | 2014-12-30 |
| 8913740 | Method and apparatus for generating an Advanced Encryption Standard (AES) key schedule | Martin G. Dixon, Srinivas Chennupaty, Mayank Bomb, Brent R. Boswell | 2014-12-16 |
| 8879725 | Combining instructions including an instruction that performs a sequence of transformations to isolate one transformation | Zeev Sperber | 2014-11-04 |
| 8869294 | Mitigating branch prediction and other timing based side channel attacks | Julien Sebot | 2014-10-21 |
| 8856547 | Speed up secure hash algorithm (SHA) using single instruction multiple data (SIMD) architectures | Vlad Krasnov | 2014-10-07 |
| 8856546 | Speed up secure hash algorithm (SHA) using single instruction multiple data (SIMD) architectures | Vlad Krasnov | 2014-10-07 |
| 8855299 | Executing an encryption instruction using stored round keys | Martin G. Dixon, Srinivas Chennupaty | 2014-10-07 |
| 8832457 | Methods and apparatus for authenticating components of processing systems | Mohan J. Kumar | 2014-09-09 |
| 8804951 | Speeding up galois counter mode (GCM) computations | Michael E. Kounavis | 2014-08-12 |
| 8799343 | Modular exponentiation with partitioned and scattered storage of Montgomery Multiplication results | Vlad Krasnov | 2014-08-05 |
| 8787565 | Method and apparatus for generating an advanced encryption standard (AES) key schedule | Martin G. Dixon, Srinivas Chennupaty, Mayank Bomb, Brent R. Boswell | 2014-07-22 |
| 8776248 | Method and apparatus for booting a processing system | Konstantin Levit-Gurevich, Boaz Ouriel, Israel Hirsh | 2014-07-08 |
| 8732548 | Instruction-set architecture for programmable cyclic redundancy check (CRC) computations | Vinodh Gopal, Gilbert M. Wolrich, Wajdi K. Feghali, Kirk S. Yap, Bradley A. Burres | 2014-05-20 |
| 8689078 | Determining a message residue | Vinodh Gopal, Wajdi K. Feghali, Gilbert M. Wolrich | 2014-04-01 |