Issued Patents All Time
Showing 26–43 of 43 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10296416 | Read from memory instructions, processors, methods, and systems, that do not take exception on defective data | Ashok Raj, Ron Gabor, Hisham Shafi, Sergiu D. Ghetie, Mohan J. Kumar +2 more | 2019-05-21 |
| 10162761 | Apparatus and method for system physical address to memory module address translation | Ashok Raj, Sreenivas Mandava, Mohan J. Kumar, Theodros Yigzaw, Ronald N. Story | 2018-12-25 |
| 10078522 | Computing platform interface with memory management | Mohan J. Kumar, Neelam Chandwani | 2018-09-18 |
| 10019354 | Apparatus and method for fast cache flushing including determining whether data is to be stored in nonvolatile memory | Mohan J. Kumar, Eswaramoorthi Nallusamy | 2018-07-10 |
| 10007528 | Computing platform interface with memory management | Guy M. Therien, Paul S. Diefenbaugh, Anil Aggarwal, Andrew D. Henroid, Jeremy J. Shrall +9 more | 2018-06-26 |
| 9645829 | Techniques to communicate with a controller for a non-volatile dual in-line memory module | Mohan J. Kumar, Adam J. Brooks, George Vergis | 2017-05-09 |
| 9612887 | Firmware-related event notification | Mohan J. Kumar, Vincent J. Zimmer, Rajesh Poornachandran | 2017-04-04 |
| 9594570 | Computing platform with interface based error injection | Mohan J. Kumar, Jose A. Vargas | 2017-03-14 |
| 9454380 | Computing platform performance management with RAS services | Mohan J. Kumar, Jose A. Vargas | 2016-09-27 |
| 9411667 | Recovery after input/ouput error-containment events | Mohan J. Kumar, Jose A. Vargas | 2016-08-09 |
| 9311138 | System management interrupt handling for multi-core processors | Mohan J. Kumar, Michael Kinney | 2016-04-12 |
| 8762778 | Firmware assisted error handling scheme | Mohan J. Kumar | 2014-06-24 |
| 8751864 | Controlling memory redundancy in a system | Robert C. Swanson, Mahesh S. Natu, Rahul Khanna, Murugasamy K. Nachimuthu, Anil S. Keshavamurthy +1 more | 2014-06-10 |
| 8650414 | Logic device having status and control registers for recording the status and controlling the operation of memory slots such that each memory slot is identified using a bus address and port number | Gopal Mundada, Palsamy Sakthikumar | 2014-02-11 |
| 8448024 | Firmware assisted error handling scheme | Mohan J. Kumar | 2013-05-21 |
| 8407516 | Controlling memory redundancy in a system | Robert C. Swanson, Mahesh S. Natu, Rahul Khanna, Murugasamy K. Nachimuthu, Anil S. Keshavamurthy +1 more | 2013-03-26 |
| 8402186 | Bi-directional handshake for advanced reliabilty availability and serviceability | — | 2013-03-19 |
| 7725637 | Methods and apparatus for generating system management interrupts | Mohan J. Kumar, Sham M. Datta | 2010-05-25 |