Issued Patents All Time
Showing 51–75 of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9898266 | Loop vectorization methods and apparatus | Nalini Vasudevan, Jayashankar Bharadwaj, Christopher J. Hughes, Mark J. Charney, Robert Valentine +4 more | 2018-02-20 |
| 9891913 | Method and apparatus for performing conflict detection using vector comparison operations | Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Robert Valentine | 2018-02-13 |
| 9785442 | Systems, apparatuses, and methods for data speculation execution | Elmoustapha Ould-Ahmed-Vall, Christopher J. Hughes, Robert Valentine | 2017-10-10 |
| 9720827 | Providing multiple memory modes for a processor including internal memory | Avinash Sodani, Robert J. Kyanko, Richard J. Greco, Andreas Kleen, Christopher M. Cantalupo | 2017-08-01 |
| 9665368 | Systems, apparatuses, and methods for performing conflict detection and broadcasting contents of a register to data element positions of another register | Christopher J. Hughes, Mark J. Charney, Jesus Corbal, Elmoustapha Ould-Ahmed_Vall, Bret L. Toll +1 more | 2017-05-30 |
| 9513917 | Vector friendly instruction format and execution thereof | Robert Valentine, Jesus Corbal San Adrian, Roger Espasa Sans, Robert Dale Cavin, Bret L. Toll +14 more | 2016-12-06 |
| 9411592 | Vector address conflict resolution with vector population count functionality | Robert Valentine, Mark J. Charney, Jesus Corbal, Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall +1 more | 2016-08-09 |
| 9411584 | Methods, apparatus, instructions, and logic to provide vector address conflict detection functionality | Christopher J. Hughes, Elmoustapha Ould-Ahmed-Vall, Robert Valentine, Jesus Corbal, Brett L. Toll +1 more | 2016-08-09 |
| 9323531 | Systems, apparatuses, and methods for determining a trailing least significant masking bit of a writemask register | Christopher J. Hughes, Mark J. Charney, Jesus Corbal, Elmoustapha Ould-Ahmedvall, Bret L. Toll +1 more | 2016-04-26 |
| 9244677 | Loop vectorization methods and apparatus | Nalini Vasudevan, Jayashankar Bharadwaj, Christopher J. Hughes, Mark J. Charney, Robert Valentine +4 more | 2016-01-26 |
| 9069605 | Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention | Richard Hankins, Hong Wang, Gautham Chinya, Trung Diep, Shivnandan Kaushik +7 more | 2015-06-30 |
| 9015688 | Vectorization of scalar functions including vectorization annotations and vectorized function signatures matching | Xinmin Tian, Sergey Stanislavoich Kozhukhov, Sergey Preis, Robert Geva, Konstantin Anatolyevich Pyjov +3 more | 2015-04-21 |
| 8996923 | Apparatus and method to obtain information regarding suppressed faults | Christopher J. Hughes, Jesus Corbal, Mark J. Charney, Elmoustapha Ould-Ahmed-Vall, Robert Valentine | 2015-03-31 |
| 8972698 | Vector conflict instructions | Christopher J. Hughes, Mark J. Charney, Yen-Kuang Chen, Jesus Corbal, Andrew T. Forsyth +4 more | 2015-03-03 |
| 8868887 | Programmable event driven yield mechanism which may activate other threads | Hong Wang, Per Hammarlund, Xiang Zou, John Shen, Xinmin Tian +2 more | 2014-10-21 |
| 8719839 | Two way communication support for heterogenous processors of a computer platform | Shoumeng Yan, Xiaocheng Zhou, Ying Gao, Mohan Rajagopalan, Rajiv Deodhar +9 more | 2014-05-06 |
| 8612949 | Methods and apparatuses for compiler-creating helper threads for multi-threading | Shih-wei Liao, Xinmin Tian, Gerolf F. Hoflehner, Hong Wang, Daniel Lavery +3 more | 2013-12-17 |
| 8607235 | Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention | Richard Hankins, Hong Wang, Gautham Chinya, Trung Diep, Shivnandan Kaushik +7 more | 2013-12-10 |
| 8447962 | Gathering and scattering multiple data elements | Christopher J. Hughes, Yen-Kuang Chen, Mayank Bomb, Jason W. Brandt, Mark Buxton +13 more | 2013-05-21 |
| 8037465 | Thread-data affinity optimization using compiler | Xinmin Tian, David C. Sehr, Richard Grove, Wei Li, Hong Wang +3 more | 2011-10-11 |
| 7984431 | Method and apparatus for exploiting thread-level parallelism | Arun Kejariwal, Xinmin Tian, Wei Li | 2011-07-19 |
| 7657880 | Safe store for speculative helper threads | Hong Wang, Tor M. Aamodt, Per Hammarlund, John Shen, Xinmin Tian +2 more | 2010-02-02 |
| 7603546 | System, method and apparatus for dependency chain processing | Satish Narayanasamy, Hong Wang, John Shen, Roni Rosner, Yoav Almog +6 more | 2009-10-13 |
| 7571301 | Fast lock-free post-wait synchronization for exploiting parallelism on multi-core processors | Arun Kejariwal, Hideki Saito, Xinmin Tian, Sanjiv Shah, Wei Li +1 more | 2009-08-04 |
| 7549146 | Apparatus, systems, and methods for execution-driven loop splitting and load-safe code hosting | Xinmin Tian | 2009-06-16 |