Issued Patents All Time
Showing 25 most recent of 27 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7152172 | Method and apparatus for real time monitoring of user presence to prolong a portable computer battery operation time | Aaron Tsirkel, Paul Buchheit | 2006-12-19 |
| 6665805 | Method and apparatus for real time monitoring of user presence to prolong a portable computer battery operation time | Aaron Tsirkel, Paul Buchheit | 2003-12-16 |
| 6554433 | Office workspace having a multi-surface projection and a multi-camera system | — | 2003-04-29 |
| 6538649 | Computer vision control variable transformation | Gary Bradski, Ryan A. Boller | 2003-03-25 |
| 6145375 | Timing device | — | 2000-11-14 |
| 5487133 | Distance calculating neural network classifier chip and system | Chin S. Park, Jay M. Diamond, Siang-Chun The, Umberto Santoni, Kenneth R. Buckmann | 1996-01-23 |
| 5268320 | Method of increasing the accuracy of an analog circuit employing floating gate memory devices | Simon Tam | 1993-12-07 |
| 5264734 | Difference calculating neural network utilizing switched capacitors | Simon Tam, Alan Kramer | 1993-11-23 |
| 5256911 | Neural network with multiplexed snyaptic processing | Simon Tam | 1993-10-26 |
| 5146602 | Method of increasing the accuracy of an analog neural network and the like | Simon Tam | 1992-09-08 |
| 5087826 | Multi-layer neural network employing multiplexed output neurons | Simon Tam | 1992-02-11 |
| 5077230 | Method for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growth | Been-Jon Woo | 1991-12-31 |
| 5075245 | Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps | Been-Jon Woo | 1991-12-24 |
| 5075869 | Neural network exhibiting improved tolerance to temperature and power supply variations | Hernan A. Castro, Simon Tam | 1991-12-24 |
| 5055897 | Semiconductor cell for neural network and the like | George R. Canepa, Simon Tam | 1991-10-08 |
| 5028810 | Four quadrant synapse cell employing single column summing line | Hernan A. Castro | 1991-07-02 |
| 4961002 | Synapse cell employing dual gate transistor structure | Simon Tam, Hernan A. Castro | 1990-10-02 |
| 4956564 | Adaptive synapse cell providing both excitatory and inhibitory connections in an associative network | Simon Tam, Hernan A. Castro | 1990-09-11 |
| 4950917 | Semiconductor cell for neural network employing a four-quadrant multiplier | Simon Tam, Ronald G. Benson, Hernan A. Castro | 1990-08-21 |
| 4906865 | Sample and hold circuit for temporal associations in a neural network | — | 1990-03-06 |
| 4784965 | Source drain doping technique | Been-Jon Woo, Ender Hokeler, Sandra S. Lee | 1988-11-15 |
| 4780424 | Process for fabricating electrically alterable floating gate memory devices | Simon Tam | 1988-10-25 |
| 4757026 | Source drain doping technique | Been-Jon Woo, Ender Hokelek, Sandra S. Lee | 1988-07-12 |
| 4728617 | Method of fabricating a MOSFET with graded source and drain regions | Been-Jon Woo, Ender Hokelek, Sandra S. Lee | 1988-03-01 |
| 4519849 | Method of making EPROM cell with reduced programming voltage | George J. Korsh, George Perlegos, Paolo Gargini | 1985-05-28 |