Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
MH

Mark A. Holler — 27 Patents

Intel: 26 patents #1,511 of 30,777Top 5%
Milpitas, CA: #170 of 3,192 inventorsTop 6%
California: #19,967 of 386,348 inventorsTop 6%
Overall (All Time): #142,059 of 4,157,543Top 4%
27 Patents All Time
Mark A. Holler has been granted 27 US patents while listed as an inventor at Intel. The first was granted in 1983 and the most recent in December 2006. Mark A. Holler ranks #142,059 of 4,157,543 US inventors in our database (top 3.4%). Patent records list Mark A. Holler in Milpitas, CA, US.

Issued Patents All Time

Showing 1–25 of 27 patents

Patent #TitleCo-InventorsDateApprox Value ⓘ
7152172 Method and apparatus for real time monitoring of user presence to prolong a portable computer battery operation time Aaron Tsirkel, Paul Buchheit 2006-12-19 $36,683,000
6665805 Method and apparatus for real time monitoring of user presence to prolong a portable computer battery operation time Aaron Tsirkel, Paul Buchheit 2003-12-16 $48,093,000
6554433 Office workspace having a multi-surface projection and a multi-camera system 2003-04-29 $39,757,000
6538649 Computer vision control variable transformation Gary Bradski, Ryan A. Boller 2003-03-25 $42,293,000
6145375 Timing device 2000-11-14
5487133 Distance calculating neural network classifier chip and system Chin S. Park, Jay M. Diamond, Siang-Chun The, Umberto Santoni, Kenneth R. Buckmann 1996-01-23 $127,580,000
5268320 Method of increasing the accuracy of an analog circuit employing floating gate memory devices Simon Tam 1993-12-07 $217,073,000
5264734 Difference calculating neural network utilizing switched capacitors Simon Tam, Alan Kramer 1993-11-23 $32,103,000
5256911 Neural network with multiplexed snyaptic processing Simon Tam 1993-10-26 $23,202,000
5146602 Method of increasing the accuracy of an analog neural network and the like Simon Tam 1992-09-08 $60,247,000
5087826 Multi-layer neural network employing multiplexed output neurons Simon Tam 1992-02-11 $34,424,000
5077230 Method for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growth Been-Jon Woo 1991-12-31 $48,446,000
5075245 Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps Been-Jon Woo 1991-12-24 $18,350,000
5075869 Neural network exhibiting improved tolerance to temperature and power supply variations Hernan A. Castro, Simon Tam 1991-12-24 $18,350,000
5055897 Semiconductor cell for neural network and the like George R. Canepa, Simon Tam 1991-10-08 $81,433,000
5028810 Four quadrant synapse cell employing single column summing line Hernan A. Castro 1991-07-02 $79,490,000
4961002 Synapse cell employing dual gate transistor structure Simon Tam, Hernan A. Castro 1990-10-02 $45,077,000
4956564 Adaptive synapse cell providing both excitatory and inhibitory connections in an associative network Simon Tam, Hernan A. Castro 1990-09-11 $45,598,000
4950917 Semiconductor cell for neural network employing a four-quadrant multiplier Simon Tam, Ronald G. Benson, Hernan A. Castro 1990-08-21 $48,734,000
4906865 Sample and hold circuit for temporal associations in a neural network 1990-03-06 $54,082,000
4784965 Source drain doping technique Been-Jon Woo, Ender Hokeler, Sandra S. Lee 1988-11-15 $9,472,000
4780424 Process for fabricating electrically alterable floating gate memory devices Simon Tam 1988-10-25 $17,698,000
4757026 Source drain doping technique Been-Jon Woo, Ender Hokelek, Sandra S. Lee 1988-07-12 $34,993,000
4728617 Method of fabricating a MOSFET with graded source and drain regions Been-Jon Woo, Ender Hokelek, Sandra S. Lee 1988-03-01 $30,751,000
4519849 Method of making EPROM cell with reduced programming voltage George J. Korsh, George Perlegos, Paolo Gargini 1985-05-28 $26,995,000