Issued Patents All Time
Showing 1–17 of 17 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7632736 | Self-aligned contact formation utilizing sacrificial polysilicon | Max Wei | 2009-12-15 |
| 7465625 | Flash memory cell having reduced floating gate to floating gate coupling | Yudong Kim, Albert Fazio | 2008-12-16 |
| 7348618 | Flash memory cell having reduced floating gate to floating gate coupling | Yudong Kim, Albert Fazio | 2008-03-25 |
| 7015149 | Simplified dual damascene process | — | 2006-03-21 |
| 5470772 | Silicidation method for contactless EPROM related devices | — | 1995-11-28 |
| 5229631 | Erase performance improvement via dual floating gate processing | — | 1993-07-20 |
| 5210047 | Process for fabricating a flash EPROM having reduced cell size | Gregory E. Atwood, Stefan Lai, T. C. Ong | 1993-05-11 |
| 5196361 | Method of making source junction breakdown for devices with source-side erasing | Tong-Chern Ong | 1993-03-23 |
| 5147813 | Erase performance improvement via dual floating gate processing | — | 1992-09-15 |
| 5102814 | Method for improving device scalability of buried bit line flash EPROM devices having short reoxidation beaks and shallower junctions | — | 1992-04-07 |
| 5077230 | Method for improving erase characteristics of buried bit line flash EPROM devices by use of a thin nitride layer formed during field oxide growth | Mark A. Holler | 1991-12-31 |
| 5075245 | Method for improving erase characteristics of buried bit line flash EPROM devices without using sacrificial oxide growth and removal steps | Mark A. Holler | 1991-12-24 |
| 4833099 | Tungsten-silicide reoxidation process including annealing in pure nitrogen and subsequent oxidation in oxygen | — | 1989-05-23 |
| 4784965 | Source drain doping technique | Mark A. Holler, Ender Hokeler, Sandra S. Lee | 1988-11-15 |
| 4774201 | Tungsten-silicide reoxidation technique using a CVD oxide cap | Wei-Jen Lo | 1988-09-27 |
| 4757026 | Source drain doping technique | Mark A. Holler, Ender Hokelek, Sandra S. Lee | 1988-07-12 |
| 4728617 | Method of fabricating a MOSFET with graded source and drain regions | Mark A. Holler, Ender Hokelek, Sandra S. Lee | 1988-03-01 |