Issued Patents All Time
Showing 26–40 of 40 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6618791 | System and method for controlling power states of a memory device via detection of a chip select signal | Michael W. Williams | 2003-09-09 |
| 6553449 | System and method for providing concurrent row and column commands | Michael W. Williams | 2003-04-22 |
| 6535956 | Method and apparatus for automatically detecting whether a board level cache is implemented with Mcache | Brian K. Langendorf | 2003-03-18 |
| 6530006 | System and method for providing reliable transmission in a buffered memory system | Michael W. Williams, John B. Halbert, Randy M. Bonella | 2003-03-04 |
| 6507530 | Weighted throttling mechanism with rank based throttling for a memory system | Michael W. Williams, Lloyd L. Pollard, II, Nitin B. Gupte | 2003-01-14 |
| 6505282 | Method and apparatus for determining memory types of a multi-type memory subsystem where memory of the different types are accessed using column control signals with different timing characteristics | Brian K. Langendorf, Nicholas D. Wade | 2003-01-07 |
| 6493250 | Multi-tier point-to-point buffered memory interface | John B. Halbert, Chung Lam, Randy M. Bonella | 2002-12-10 |
| 6449213 | Memory interface having source-synchronous command/address signaling | Michael W. Williams, John B. Halbert, Randy M. Bonella | 2002-09-10 |
| 6442632 | System resource arbitration mechanism for a host bridge | George R. Hayek, Brian K. Langendorf, Aniruddha Kundu, Gary Solomon, Peter D. MacWilliams | 2002-08-27 |
| 6212589 | System resource arbitration mechanism for a host bridge | George R. Hayek, Brian K. Langendorf, Aniruddha Kundu, Gary Solomon, Peter D. MacWilliams | 2001-04-03 |
| 6148380 | Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus | Richard E. Malinowski | 2000-11-14 |
| 5898856 | Method and apparatus for automatically detecting a selected cache type | Brian K. Langendorf | 1999-04-27 |
| 5894567 | Mechanism for enabling multi-bit counter values to reliably cross between clocking domains | Robert N. Murdoch | 1999-04-13 |
| 5640519 | Method and apparatus to improve latency experienced by an agent under a round robin arbitration scheme | Brian K. Langendorf, George R. Hayek | 1997-06-17 |
| 5603010 | Performing speculative system memory reads prior to decoding device code | Richard E. Malinowski, Brian K. Langendorf, George R. Hayek | 1997-02-11 |