Issued Patents All Time
Showing 26–50 of 52 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7809932 | Methods and apparatus for adapting pipeline stage latency based on instruction type | Gerald George Pechanek, Patrick R. Marchand | 2010-10-05 |
| 7765338 | Methods and apparatus for providing bit-reversal and multicast functions utilizing DMA controller | Nikos P. Pitsianis, Kevin Coopman | 2010-07-27 |
| 7730280 | Methods and apparatus for independent processor node operations in a SIMD array processor | Gerald George Pechanek, Mihailo M. Stojancic | 2010-06-01 |
| 7627698 | Methods and apparatus for providing data transfer control | Edward A. Wolff | 2009-12-01 |
| RE41012 | Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor | Gerald George Pechanek, Patrick R. Marchand | 2009-11-24 |
| RE40883 | Methods and apparatus for dynamic instruction controlled reconfigurable register file with extended precision | Gerald George Pechanek | 2009-08-25 |
| 7506137 | Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions | Gerald George Pechanek, David Strube, Edward A. Wolff, Grayson Morris, Carl Donald Busboom +1 more | 2009-03-17 |
| 7386710 | Methods and apparatus for scalable array processor interrupt detection and response | Patrick R. Marchand, Gerald George Pechanek, Larry D. Larsen | 2008-06-10 |
| RE40213 | Methods and apparatus for providing direct memory access control | — | 2008-04-01 |
| 7302504 | Methods and apparatus for providing data transfer control | Edward A. Wolff | 2007-11-27 |
| 7272700 | Methods and apparatus for indirect compound VLIW execution using operand address mapping techniques | Gerald George Pechanek | 2007-09-18 |
| 7266620 | System core for transferring data between an external device and memory | Gerald George Pechanek, David Strube, Charles W. Kurak, Jr., Carl Donald Busboom, Dale Edward Schneider +6 more | 2007-09-04 |
| 7257696 | Methods and apparatus for initiating and resynchronizing multi-cycle SIMD instructions | Gerald George Pechanek, David Strube, Edward A. Wolff, Grayson Morris, Carl Donald Busboom +1 more | 2007-08-14 |
| 7254695 | Coprocessor processing instructions in turn from multiple instruction ports coupled to respective processors | — | 2007-08-07 |
| 7237088 | Methods and apparatus for providing context switching between software tasks with reconfigurable control | Gerald George Pechanek, David Strube | 2007-06-26 |
| 7146487 | Methods and apparatus to support conditional execution in a VLIW-based array processor with subword execution | Thomas L. Drabenstott, Gerald George Pechanek, Charles W. Kurak, Jr. | 2006-12-05 |
| 7130934 | Methods and apparatus for providing data transfer control | Edward A. Wolff | 2006-10-31 |
| 7058790 | Cascaded event detection modules for generating combined events interrupt for processor action | Patrick R. Marchand, Gerald George Pechanek, Charles W. Kurak, Jr. | 2006-06-06 |
| 6912608 | Methods and apparatus for pipelined bus | Edward A. Wolff, David Eugene Baker, Bryan Cope | 2005-06-28 |
| 6851041 | Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor | Gerald George Pechanek, Juan Guillermo Revilla | 2005-02-01 |
| 6848041 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Gerald George Pechanek, Juan Guillermo Revilla, Larry D. Larsen | 2005-01-25 |
| 6775766 | Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor | Juan Guillermo Revilla, Patrick R. Marchand, Gerald George Pechanek | 2004-08-10 |
| 6735690 | Specifying different type generalized event and action pair in a processor | Patrick R. Marchand, Gerald George Pechanek, Charles W. Kurak, Jr. | 2004-05-11 |
| 6557094 | Methods and apparatus for scalable instruction set architecture with dynamic compact instructions | Gerald George Pechanek, Juan Guillermo Revilla, Larry D. Larsen | 2003-04-29 |
| 6446190 | Register file indexing methods and apparatus for providing indirect control of register addressing in a VLIW processor | Gerald George Pechanek, Patrick R. Marchand | 2002-09-03 |