Issued Patents All Time
Showing 26–50 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8589849 | Method and apparatus for implementing soft constraints in tools used for designing programmable logic devices | Terry Borer, Gabriel Quan, Stephen D. Brown, Chris G. Sanford, Vaughn Betz +2 more | 2013-11-19 |
| 8510688 | Method and apparatus for performing multiple stage physical synthesis | Valavan Manohararajah, Gordon Raymond Chiu, Ivan Blunno, Stephen D. Brown | 2013-08-13 |
| 8499201 | Methods and systems for measuring and presenting performance data of a memory controller system | Gordon Raymond Chiu, Joshua David Fender, Clement Tse | 2013-07-30 |
| 8484596 | Method and apparatus for performing fast incremental resynthesis | Doris Tzu Lang Chen | 2013-07-09 |
| 8296695 | Method and apparatus for performing fast incremental resynthesis | Doris Tzu Lang Chen | 2012-10-23 |
| 8296696 | Method and apparatus for performing simultaneous register retiming and combinational resynthesis during physical synthesis | Gordon Raymond Chiu, Valavan Manohararajah, Ivan Blunno, Stephen D. Brown | 2012-10-23 |
| 8214701 | Hardware and software debugging | Shawn Malhotra | 2012-07-03 |
| 8095914 | Methods for instruction trace decomposition | Stephen D. Brown | 2012-01-10 |
| 8032855 | Method and apparatus for performing incremental placement on a structured application specific integrated circuit | Andrew Chaang Ling | 2011-10-04 |
| 7996797 | Method and apparatus for performing multiple stage physical synthesis | Valavan Manohararajah, Gordon Raymond Chiu, Ivan Blunno, Stephen D. Brown | 2011-08-09 |
| 7797666 | Systems and methods for mapping arbitrary logic functions into synchronous embedded memories | Gordon Raymond Chiu, Valavan Manohararajah, Stephen D. Brown | 2010-09-14 |
| 7620925 | Method and apparatus for performing post-placement routability optimization | Valavan Manohararajah, Gordon Raymond Chiu, Stephen D. Brown | 2009-11-17 |
| 7594204 | Method and apparatus for performing layout-driven optimizations on field programmable gate arrays | Paul McHardy, Chris G. Sanford, Gabriel Quan, Terry Borer, Ian Chesal +3 more | 2009-09-22 |
| 7509597 | Method and apparatus for performing post-placement functional decomposition on field programmable gate arrays using binary decision diagrams | Valavan Manohararajah, Stephen D. Brown | 2009-03-24 |
| 7500216 | Method and apparatus for performing physical synthesis hill-climbing on multi-processor machines | Ivan Blunno, Gordon Raymond Chiu, Valavan Manohararajah, Stephen D. Brown | 2009-03-03 |
| 7464286 | Programmable logic devices with skewed clocking signals | Andrew Hall | 2008-12-09 |
| 7444613 | Systems and methods for mapping arbitrary logic functions into synchronous embedded memories | Gordon Raymond Chiu, Valavan Manohararajah, Stephen D. Brown | 2008-10-28 |
| 7412677 | Detecting reducible registers | Valavan Manohararajah, Gordon Raymond Chiu, Stephen D. Brown | 2008-08-12 |
| 7401314 | Method and apparatus for performing compound duplication of components on field programmable gate arrays | Karl Schabas, Stephen D. Brown, Terry Borer, Shawn Malhotra | 2008-07-15 |
| 7360190 | Method and apparatus for performing retiming on field programmable gate arrays | Gabriel Quan, Terry Borer, Ian Chesal, Valavan Manohararajah, Karl Schabas +1 more | 2008-04-15 |
| 7318210 | Method and apparatus for performing incremental placement for layout-driven optimizations on field programmable gate arrays | Stephen D. Brown | 2008-01-08 |
| 7290240 | Leveraging combinations of synthesis, placement and incremental optimizations | Carolyn Lam-Leventis, Terry Borer | 2007-10-30 |
| 7290239 | Method and apparatus for performing post-placement functional decomposition for field programmable gate arrays | Valavan Manohararajah, Karl Schabas | 2007-10-30 |
| 7257800 | Method and apparatus for performing logic replication in field programmable gate arrays | Gabriel Quan, Terry Borer, Valavan Manohararajah, Paul McHardy, Ivan Hamer +2 more | 2007-08-14 |
| 7254801 | Synthesis aware placement: a novel approach that combines knowledge of possible resynthesis | Terry Borer, Stephen D. Brown | 2007-08-07 |