Issued Patents All Time
Showing 51–75 of 88 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9049125 | General input/output architecture, protocol and related methods to implement flow control | Jasmin Ajanovic, David J. Harriman, David M. Lee | 2015-06-02 |
| 8929373 | Sending packets with expanded headers | Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Rohit Verma, Robert P. Adler | 2015-01-06 |
| 8874976 | Providing error handling support to legacy devices | Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Rohit Verma | 2014-10-28 |
| 8819306 | General input/output architecture with PCI express protocol with credit-based flow control | Jasmin Ajanovic, David J. Harriman, David M. Lee | 2014-08-26 |
| 8805926 | Common idle state, active state and credit management for an interface | Sridhar Lakshmanamurthy, Robert P. Adler, Mikal C. Hunsaker, Michael T. Klinglesmith, Eran Tamari +2 more | 2014-08-12 |
| 8775700 | Issuing requests to a fabric | Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Eran Tamari, Joseph Murray +2 more | 2014-07-08 |
| 8711875 | Aggregating completion messages in a sideband interface | Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Mohan Nair, Joseph Murray +3 more | 2014-04-29 |
| 8713240 | Providing multiple decode options for a system-on-chip (SoC) fabric | Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Eran Tamari, Joseph Murray +1 more | 2014-04-29 |
| 8713234 | Supporting multiple channels of a single interface | Sridhar Lakshmanamurthy, Mikal C. Hunsaker, Michael T. Klinglesmith, Eran Tamari, Joseph Murray +1 more | 2014-04-29 |
| 8566473 | General input/output architecture, protocol and related methods to implement flow control | Jasmin Ajanovic, David J. Harriman, David M. Lee | 2013-10-22 |
| 7877619 | Power mode control method and circuitry | Ramana Rachakonda, Anil K. Sabbavarapu, Belliappa Kuttanna, Rajesh Patel, Kenneth D. Shoemaker +3 more | 2011-01-25 |
| 7725751 | Termination techniques for bus interfaces | Binta M. Patel | 2010-05-25 |
| 7536473 | General input/output architecture, protocol and related methods to implement flow control | Jasmin Ajanovic, David J. Harriman, David M. Lee | 2009-05-19 |
| 7353313 | General input/output architecture, protocol and related methods to manage data integrity | Eric R. Wehage, Jasmin Ajanovic, David J. Harriman, David M. Lee, Buck Gremel +2 more | 2008-04-01 |
| 7313653 | Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device | — | 2007-12-25 |
| 7213107 | Dedicated cache memory | — | 2007-05-01 |
| 7152128 | General input/output architecture, protocol and related methods to manage data integrity | Eric R. Wehage, Jasmin Ajanovic, David J. Harriman, David M. Lee, Buck Gremel +2 more | 2006-12-19 |
| 7017008 | Method and apparatus for optimizing data streaming in a computer system utilizing random access memory in a system logic device | — | 2006-03-21 |
| 6968410 | Multi-threaded processing of system management interrupts | Joseph A. Bennett | 2005-11-22 |
| 6918001 | Point-to-point busing and arrangement | — | 2005-07-12 |
| 6918060 | Bounding data transmission latency based upon link loading and arrangement | — | 2005-07-12 |
| 6904499 | Controlling cache memory in external chipset using processor | — | 2005-06-07 |
| 6880111 | Bounding data transmission latency based upon a data transmission event and arrangement | — | 2005-04-12 |
| 6816986 | Remapping memory devices during operation | — | 2004-11-09 |
| 6701469 | Detecting and handling bus errors in a computer system | Eugene P. Matter | 2004-03-02 |