Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10430267 | Determine when an error log was created | Narayan Ranganathan | 2019-10-01 |
| 10387072 | Systems and method for dynamic address based mirroring | Sarathy Jayakumar, Mohan J. Kumar, Hemalatha Gurumoorthy, Ronald N. Story | 2019-08-20 |
| 10324852 | System and method to increase availability in a multi-level memory configuration | Theodros Yigzaw, Robert C. Swanson, Mohan J. Kumar | 2019-06-18 |
| 10318368 | Enabling error status and reporting in a machine check architecture | Theodros Yigzaw | 2019-06-11 |
| 10319458 | Hardware apparatuses and methods to check data storage devices for transient faults | Ron Gabor, Hisham Shafi, Mohan J. Kumar, Theodros Yigzaw | 2019-06-11 |
| 10296416 | Read from memory instructions, processors, methods, and systems, that do not take exception on defective data | Ron Gabor, Hisham Shafi, Sergiu D. Ghetie, Mohan J. Kumar, Theodros Yigzaw +2 more | 2019-05-21 |
| 10223187 | Instruction and logic to expose error domain topology to facilitate failure isolation in a processor | Narayan Ranganathan, Mohan J. Kumar, Vincent J. Zimmer | 2019-03-05 |
| 10185619 | Handling of error prone cache line slots of memory side cache of multi-level system memory | Theodros Yigzaw, Robert C. Swanson, Mohan J. Kumar | 2019-01-22 |
| 10162761 | Apparatus and method for system physical address to memory module address translation | Sreenivas Mandava, Sarathy Jayakumar, Mohan J. Kumar, Theodros Yigzaw, Ronald N. Story | 2018-12-25 |
| 10157142 | Offload data transfer engine for a block data transfer interface | Sivakumar Radhakrishnan, Dan Williams, Vishal Verma, Narayan Ranganathan, Chet R. Douglas | 2018-12-18 |
| 9904586 | Interfacing with block-based storage in a processor | Theodros Yigzaw, Mohan J. Kumar, Hisham Shafi, Ron Gabor | 2018-02-27 |
| 9864603 | Instruction and logic for machine check interrupt management | Mohan J. Kumar | 2018-01-09 |
| 9842015 | Instruction and logic for machine checking communication | Mohan J. Kumar, Jose A. Vargas, William G. Auld, Cameron McNairy, Theodros Yigzaw +2 more | 2017-12-12 |
| 9652747 | Context based alert system | — | 2017-05-16 |
| 9595349 | Hardware apparatuses and methods to check data storage devices for transient faults | Ron Gabor, Hisham Shafi, Mohan J. Kumar, Theodros Yigzaw | 2017-03-14 |
| 9396059 | Exchange error information from platform firmware to operating system | Mohan J. Kumar, Narayan Ranganathan | 2016-07-19 |
| 9389942 | Determine when an error log was created | Narayan Ranganathan | 2016-07-12 |
| 9384076 | Allocating machine check architecture banks | William G. Auld, Malini K. Bhandaru | 2016-07-05 |
| 9141454 | Signaling software recoverable errors | John G. Holm, Gilbert Neiger, Rajesh M. Sankaran, Mohan J. Kumar | 2015-09-22 |
| 8671309 | Mechanism for advanced server machine check recovery and associated system software enhancements | Narayan Ranganathan, Mohan J. Kumar, Theodros Yigzaw | 2014-03-11 |
| 7636832 | I/O translation lookaside buffer performance | Rajesh Shah | 2009-12-22 |
| 7447820 | Retargeting of platform interrupts | — | 2008-11-04 |
| 7194540 | Mechanism for allowing multiple entities on the same host to handle messages of same service class in a cluster | Anil Aggarwal, Oscar P. Pinto, Bruce Schlobohm, Rajesh Shah | 2007-03-20 |
| 7039922 | Cluster with multiple paths between hosts and I/O controllers | Rajesh Shah | 2006-05-02 |
| 6772320 | Method and computer program for data conversion in a heterogeneous communications network | — | 2004-08-03 |