Issued Patents All Time
Showing 25 most recent of 36 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12189775 | Seamless firmware update mechanism | Ned M. Smith, Xiaoyu Ruan | 2025-01-07 |
| 12183412 | Method and apparatus for enabling multiple return material authorizations (RMAs) on an integrated circuit device | Sankaran M. Menon, Ting Lu, Kenneth Chen, Wei Chun Lau | 2024-12-31 |
| 12010144 | End-to-end device attestation | Ned M. Smith, Jose Benchimol | 2024-06-11 |
| 11562101 | On-device bitstream validation | Scott J. Weber, Sean R. Atsatt, David Samuel Goldman | 2023-01-24 |
| 11281383 | Side-channel attack resistant fuse programming | Ting Lu, Sean R. Atsatt, Eric Innis | 2022-03-22 |
| 10659052 | Regional partial reconfiguration of a programmable device | Sean R. Atsatt | 2020-05-19 |
| 10444283 | Sharing a JTAG interface among multiple partitions | Yi Peng, Nathan Edward Krueger | 2019-10-15 |
| 10223014 | Maintaining reconfigurable partitions in a programmable device | Sean R. Atsatt, Ting Lu, Steve Vu, Scott J. Weber | 2019-03-05 |
| 10218359 | Regional partial reconfiguration of a programmable device | Sean R. Atsatt | 2019-02-26 |
| 9404968 | System and methods for debug connectivity discovery | — | 2016-08-02 |
| 9191617 | Using FPGA partial reconfiguration for codec applications | Russell A. James | 2015-11-17 |
| 8412918 | Booting mechanism for FPGA-based embedded system | Timothy P. Allen, Aaron Ferrucci, Kerry Veenstra | 2013-04-02 |
| 8190828 | Embedded processor with dual-port SRAM for programmable logic | Roger May, Paul Metzgen, Neil Thorne | 2012-05-29 |
| 8069286 | Flexible on-chip datapath interface having first and second component interfaces wherein communication is determined based on a type of credit condition | Kent Orthner, Desmond Ambrose | 2011-11-29 |
| 7844761 | Flexible on-chip datapath interface for facilitating communication between first and second interfaces with different interface properties | Kent Orthner, Desmond Ambrose | 2010-11-30 |
| 7822958 | Booting mechanism for FPGA-based embedded system | Timothy P. Allen, Aaron Ferrucci, Kerry Veenstra | 2010-10-26 |
| 7657689 | Methods and apparatus for handling reset events in a bus bridge | Andrew Crosland | 2010-02-02 |
| 7584348 | Techniques for configuring an embedded processor operating system | Iain Scott, Paul M. Riley | 2009-09-01 |
| 7549004 | Split filtering in multilayer systems | Fabio P Sousa | 2009-06-16 |
| 7546424 | Embedded processor with dual-port SRAM for programmable logic | Roger May, Paul Metzgen, Neil Thorne | 2009-06-09 |
| 7412624 | Methods and apparatus for debugging a system with a hung data bus | — | 2008-08-12 |
| 7350178 | Embedded processor with watchdog timer for programmable logic | Andrew Crosland, Roger May, Edward Flaherty | 2008-03-25 |
| 7343483 | Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream | Roger May | 2008-03-11 |
| 7340596 | Embedded processor with watchdog timer for programmable logic | Andrew Crosland, Roger May, Edward Flaherty | 2008-03-04 |
| 7321996 | Digital data error insertion methods and apparatus | Kulwinder Dhanoa | 2008-01-22 |