Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11431646 | Systems and methods for predictive scheduling and rate limiting | — | 2022-08-30 |
| 10834009 | Systems and methods for predictive scheduling and rate limiting | — | 2020-11-10 |
| 9424210 | SDRAM memory organization and efficient access | Benjamin Thomas Cope, Lei Xu | 2016-08-23 |
| 9000802 | Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device | Michael Fitton, Benjamin Thomas Cope, Kellie Marks, Lei Xu | 2015-04-07 |
| 8782115 | Hardware architecture and scheduling for high performance and low resource solution for QR decomposition | — | 2014-07-15 |
| 8731078 | Downlink subchannelization module | Mehul Mehta | 2014-05-20 |
| 8629691 | Systems and methods for interfacing between hard logic and soft logic in a hybrid integrated device | Michael Fitton, Benjamin Thomas Cope, Kellie Marks, Lei Xu | 2014-01-14 |
| 8548078 | Ranging code detection | Michael Fitton, Mehul Mehta | 2013-10-01 |
| 8539014 | Solving linear matrices in an integrated circuit device | Martin Langhammer | 2013-09-17 |
| 8307021 | Hardware architecture and scheduling for high performance solution to cholesky decomposition | Michael Fitton | 2012-11-06 |
| 8121203 | Ranging code detection | Michael Fitton, Mehul Mehta | 2012-02-21 |
| 8005177 | Peak windowing for crest factor reduction | Volker Mauer, Paul Metzgen | 2011-08-23 |
| 7983350 | Downlink subchannelization module | Mehul Mehta | 2011-07-19 |
| 7954015 | Data interleaving and deinterleaving involving concatenation of words read from storage | — | 2011-05-31 |
| 7899957 | Memory controller having a buffer for providing beginning and end data | — | 2011-03-01 |
| 7586995 | Peak windowing for crest factor reduction | Volker Mauer, Paul Metzgen | 2009-09-08 |
| 7321996 | Digital data error insertion methods and apparatus | Andrew Draper | 2008-01-22 |
| 7159084 | Memory controller | — | 2007-01-02 |
| 6828822 | Apparatus and methods for shared memory interfaces in programmable logic devices | Andrew Bellis, Andrew Draper | 2004-12-07 |