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Single chip multi-die architecture having safety-compliant cross-monitoring capability |
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Two die system on chip (SoC) for providing hardware fault tolerance (HFT) for a paired SoC |
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Testing an integrated circuit in user mode using partial reconfiguration |
Adam Titley |
2018-07-10 |
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Video processing architecture |
Andrew Crosland |
2015-07-14 |
| 8190828 |
Embedded processor with dual-port SRAM for programmable logic |
Andrew Draper, Paul Metzgen, Neil Thorne |
2012-05-29 |
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SDRAM controller |
— |
2011-03-29 |
| 7546424 |
Embedded processor with dual-port SRAM for programmable logic |
Andrew Draper, Paul Metzgen, Neil Thorne |
2009-06-09 |
| 7446561 |
I/O circuitry shared between processor and programmable logic portions of an integrated circuit |
Igor Kostarnov, Edward Flaherty, Mark Dickinson |
2008-11-04 |
| 7350178 |
Embedded processor with watchdog timer for programmable logic |
Andrew Crosland, Edward Flaherty, Andrew Draper |
2008-03-25 |
| 7343483 |
Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream |
Andrew Draper |
2008-03-11 |
| 7340596 |
Embedded processor with watchdog timer for programmable logic |
Andrew Crosland, Edward Flaherty, Andrew Draper |
2008-03-04 |
| 7096324 |
Embedded processor with dual-port SRAM for programmable logic |
Andrew Draper, Paul Metzgen, Neil Thorne |
2006-08-22 |
| 7081773 |
Updating configuration for programmable logic device |
James Tyson, Mark Dickinson |
2006-07-25 |
| 7064578 |
Distributed bus structure |
Andrew Crosland, Stephane Caneau, Andrew Draper, Edward Flaherty |
2006-06-20 |
| 7026840 |
Programmable logic device |
Andrew Crosland, Edward Flaherty |
2006-04-11 |
| 6980024 |
I/O circuitry shared between processor and programmable logic portions of an integrated circuit |
Igor Kostarnov, Edward Flaherty, Mark Dickinson |
2005-12-27 |
| 6937061 |
Address decoder for programmable logic device |
Andrew Crosland, Stephane Cauneau, Andrew Draper, Edward Flaherty |
2005-08-30 |
| 6803785 |
I/O circuitry shared between processor and programmable logic portions of an integrated circuit |
Igor Kostarnov, Edward Flaherty, Mark Dickinson |
2004-10-12 |
| 6745369 |
Bus architecture for system on a chip |
James Tyson, Edward Flaherty, Mark Dickinson |
2004-06-01 |
| 6732263 |
Configuring both a programmable logic device and its embedded logic with a single serialized configuration bit stream |
Andrew Draper |
2004-05-04 |
| 4928258 |
Recursive median filtering |
— |
1990-05-22 |
| H713 |
Automatic target detection and recognition |
Frank B. Link |
1989-11-07 |
| 4814884 |
Window generator |
William K. Johnson, III |
1989-03-21 |
| 4679086 |
Motion sensitive frame integration |
— |
1987-07-07 |