Issued Patents All Time
Showing 51–75 of 153 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6781857 | Content addressable memory (CAM) devices that utilize multi-port CAM cells and control logic to support multiple overlapping search cycles that are asynchronously timed relative to each other | Chau-Chin Wu, Mark Baumann | 2004-08-24 |
| 6754093 | CAM circuit with radiation resistance | — | 2004-06-22 |
| 6724601 | ESD protection circuit | Chau-Chin Wu, Ta-Ke Tien | 2004-04-20 |
| 6700827 | Cam circuit with error correction | Michael J. Miller | 2004-03-02 |
| 6661687 | Cam circuit with separate memory and logic operating voltages | Chau-Chin Wu | 2003-12-09 |
| 6657878 | Content addressable memory (CAM) devices having reliable column redundancy characteristics and methods of operating same | Chau-Chin Wu | 2003-12-02 |
| 6576976 | Semiconductor integrated circuit with an insulation structure having reduced permittivity | S. Kevin Lee | 2003-06-10 |
| 6570405 | Integrated output driver circuits having current sourcing and current sinking characteristics that inhibit power bounce and ground bounce | — | 2003-05-27 |
| 6566236 | Gate structures with increased etch margin for self-aligned contact and the method of forming the same | Tsengyou Syau, Guo-Qiang Lo, Shih-Ked Lee, Sang-Yun Lee, Ching-Kai Lin | 2003-05-20 |
| 6563754 | DRAM circuit with separate refresh memory | Chau-Chin Wu | 2003-05-13 |
| 6560156 | CAM circuit with radiation resistance | Michael J. Miller | 2003-05-06 |
| 6534414 | Dual-mask etch of dual-poly gate in CMOS processing | Kuilong Wang, Tsengyou Syau, Shih-Ked Lee | 2003-03-18 |
| 6512685 | CAM circuit with separate memory and logic operating voltages | Chau-Chin Wu | 2003-01-28 |
| 6505271 | Increasing priority encoder speed using the most significant bit of a priority address | Chau-Chin Wu | 2003-01-07 |
| 6470418 | Pipelining a content addressable memory cell array for low-power operation | Chau-Chin Wu, John R. Mick | 2002-10-22 |
| 6441651 | High voltage tolerable input buffer | — | 2002-08-27 |
| 6421265 | DRAM-based CAM cell using 3T or 4T DRAM cells | Chau-Chin Wu, Ta-Ke Tien | 2002-07-16 |
| 6400593 | Ternary CAM cell with DRAM mask circuit | Chau-Chin Wu | 2002-06-04 |
| 6372641 | Method of forming self-aligned via structure | — | 2002-04-16 |
| 6373739 | Quad CAM cell with minimum cell size | Chau-Chin Wu | 2002-04-16 |
| 6350645 | Strapping via for interconnecting integrated circuit structures | Kyle Terrill | 2002-02-26 |
| 6333524 | Electrically programmable interlevel fusible link for integrated circuits | Anita M. Hansen, David J. Pilling | 2001-12-25 |
| 6307399 | High speed buffer circuit with improved noise immunity | Ta-Ke Tien | 2001-10-23 |
| 6278162 | ESD protection for LDD devices | Paul Y. M. Shy | 2001-08-21 |
| 6266263 | CAM array with minimum cell size | Chau-Chin Wu | 2001-07-24 |