Issued Patents All Time
Showing 301–311 of 311 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6321306 | High performance multiprocessor system with modified-unsolicited cache state | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie | 2001-11-20 |
| 6314498 | Multiprocessor system bus transaction for transferring exclusive-deallocate cache state to lower lever cache | Ravi Kumar Arimilli, Lakshminarayana B. Arimilli, John Steven Dodson, Guy L. Guthrie | 2001-11-06 |
| 6075937 | Preprocessing of stored target routines for controlling emulation of incompatible instructions on a target processor and utilizing target processor feedback for controlling non-sequential incompatible instruction emulation | Casper A. Scalzi, Eric M. Schwarz, James R. Urquhart, Douglas W. Westcott | 2000-06-13 |
| 6009261 | Preprocessing of stored target routines for emulating incompatible instructions on a target processor | Casper A. Scalzi, Eric M. Schwarz, James R. Urquhart, Douglas W. Westcott | 1999-12-28 |
| 5894575 | Method and system for initial state determination for instruction trace reconstruction | Frank Eliot Levine, Bradley McCredie, Edward Hugh Welbon | 1999-04-13 |
| 5889947 | Apparatus and method for executing instructions that select a storage location for output values in response to an operation count | — | 1999-03-30 |
| 5878208 | Method and system for instruction trace reconstruction utilizing limited output pins and bus monitoring | Frank Eliot Levine, Edward Hugh Welbon | 1999-03-02 |
| 5862371 | Method and system for instruction trace reconstruction utilizing performance monitor outputs and bus monitoring | Frank Eliot Levine, Edward Hugh Welbon, Jack Chris Randolph | 1999-01-19 |
| 5809566 | Automatic cache prefetch timing with dynamic trigger migration | Mark J. Charney, Pradeep Kumar Dubey, Thomas R. Puzak | 1998-09-15 |
| 5577231 | Storage access authorization controls in a computer system using dynamic translation of large addresses | Casper A. Scalzi | 1996-11-19 |
| 5560013 | Method of using a target processor to execute programs of a source architecture that uses multiple address spaces | Casper A. Scalzi | 1996-09-24 |