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USPTO Patent Rankings Data through Sept 30, 2025
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Timothy J. Dell — 95 Patents

IBM: 94 patents #629 of 70,183Top 1%
Colchester, VT: #7 of 432 inventorsTop 2%
Vermont: #57 of 4,968 inventorsTop 2%
Overall (All Time): #16,149 of 4,157,543Top 1%
95 Patents All Time

Issued Patents All Time

Showing 26–50 of 95 patents

Patent #TitleCo-InventorsDate
9043569 Memory data management Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi 2015-05-26
9015522 Implementing DRAM failure scenarios mitigation by using buffer techniques delaying usage of RAS features in computer systems Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi 2015-04-21
8996953 Self monitoring and self repairing ECC Edgar R. Cordero, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow, Saravanan Sethuraman 2015-03-31
8996935 Memory operation of paired memory devices Edgar R. Cordero, Girisankar Paulraj, Saravanan Sethuraman 2015-03-31
8964495 Memory operation upon failure of one of two paired memory devices Edgar R. Cordero, Girisankar Paulraj, Saravanan Sethuraman 2015-02-24
8848470 Memory operation upon failure of one of two paired memory devices Edgar R. Cordero, Girisankar Paulraj, Saravanan Sethuraman 2014-09-30
8589769 System, method and storage medium for providing fault detection and correction in a memory subsystem Kevin C. Gower, Warren E. Maule 2013-11-19
8359521 Providing a memory device having a shared error feedback pin Kyu-hyoun Kim, Paul W. Coteus 2013-01-22
8245105 Cascade interconnect memory system with enhanced reliability Kevin C. Gower, Warren E. Maule, Michael R. Trombley 2012-08-14
8201069 Cyclical redundancy code for use in a high-speed serial link Kevin C. Gower, Luis A. Lastras-Montano 2012-06-12
8185801 System to improve error code decoding using historical information and associated methods Luis A. Lastras-Montano, Barry M. Trager, Shmuel Winograd 2012-05-22
8176391 System to improve miscorrection rates in error control code through buffering and associated methods Irving G. Baysah, Luis A. Lastras-Montano, Warren E. Maule, Eric E. Retter, Barry M. Trager +3 more 2012-05-08
8171377 System to improve memory reliability and associated methods Luis A. Lastras-Montano, Barry M. Trager, Shmuel Winograd 2012-05-01
8140942 System, method and storage medium for providing fault detection and correction in a memory subsystem Kevin C. Gower, Warren E. Maule 2012-03-20
8041990 System and method for error correction and detection in a memory system James A. O'Connor, Luis A. Lastras-Montano, Luis C. Alves, William J. Clarke, Thomas J. Dewkett +1 more 2011-10-18
8041989 System and method for providing a high fault tolerant memory system Luis A. Lastras-Montano, James A. O'Connor, Luiz C. Alves, William J. Clarke, Thomas J. Dewkett +1 more 2011-10-18
7996747 Forward error correction encoding for multiple link transmission compatible with 64B/66B scrambling Rene Glaise 2011-08-09
7840860 Double DRAM bit steering for multiple error corrections Luiz C. Alves, Mark A. Brittain, Sanjeev Ghai, Warren E. Maule, Scott Barnett Swaney 2010-11-23
7721140 Systems and methods for improving serviceability of a memory system Luis A. Lastras-Montano 2010-05-18
7721178 Systems, methods, and computer program products for providing a two-bit symbol bus error correcting code Patrick J. Meaney 2010-05-18
7712010 Systems, methods and computer program products for utilizing a spare lane for additional checkbits 2010-05-04
7539800 System, method and storage medium for providing segment level sparing Frank D. Ferraiolo, Kevin C. Gower, Kevin W. Kark, Mark W. Kellogg, Warren E. Maule 2009-05-26
7523364 Double DRAM bit steering for multiple error corrections Luiz C. Alves, Mark A. Brittain, Sanjeev Ghai, Warren E. Maule, Scott Barnett Swaney 2009-04-21
7484161 System, method and storage medium for providing fault detection and correction in a memory subsystem Kevin C. Gower, Warren E. Maule 2009-01-27
7331010 System, method and storage medium for providing fault detection and correction in a memory subsystem Kevin C. Gower, Warren E. Maule 2008-02-12