Issued Patents All Time
Showing 76–99 of 99 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9305619 | Implementing simultaneous read and write operations utilizing dual port DRAM | Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow | 2016-04-05 |
| 9305618 | Implementing simultaneous read and write operations utilizing dual port DRAM | Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow | 2016-04-05 |
| 9298201 | Power delivery to three-dimensional chips | Vijay Anand Mathiyalagan, Siva Rama K. Pullelli, Kenneth L. Wright | 2016-03-29 |
| 9263157 | Detecting defective connections in stacked memory devices | Charles A. Kilmer, Warren E. Maule | 2016-02-16 |
| 9251054 | Implementing enhanced reliability of systems utilizing dual port DRAM | Edgar R. Cordero, Carlos A. Fernandez, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow | 2016-02-02 |
| 9252131 | Chip stack cache extension with coherency | Edgar R. Cordero, Anand Haridass, Subrat K. Panda, Diyanesh Babu C. Vidyapoornachary | 2016-02-02 |
| 9230687 | Implementing ECC redundancy using reconfigurable logic blocks | Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow | 2016-01-05 |
| 9147499 | Memory operation of paired memory devices | Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj | 2015-09-29 |
| 9128887 | Using a buffer to replace failed memory cells in a memory component | Manoj Dusanapudi, Prasanna Jayaraman, Anil B. Lingambudi, Girisankar Paulraj, Diyanesh Babu C. Vidyapoornachary | 2015-09-08 |
| 9021411 | Characterizing TSV structures in a semiconductor chip stack | Anand Haridass, Subramanian S. Iyer, Ming Yin | 2015-04-28 |
| 8996935 | Memory operation of paired memory devices | Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj | 2015-03-31 |
| 8996953 | Self monitoring and self repairing ECC | Edgar R. Cordero, Timothy J. Dell, Joab D. Henderson, Jeffrey A. Sabrowski, Anuwat Saetow | 2015-03-31 |
| 8964495 | Memory operation upon failure of one of two paired memory devices | Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj | 2015-02-24 |
| 8902750 | Translating between an ethernet protocol and a converged enhanced ethernet protocol | Claude Basso, Anil Pothireddy, Christoph Raisch, Vibhor K. Srivastava, Jan-Bernd Themann +1 more | 2014-12-02 |
| 8872322 | Stacked chip module with integrated circuit chips having integratable built-in self-maintenance blocks | Kevin W. Gorman, Derek H. Leu, Krishnendu Mondal | 2014-10-28 |
| 8874979 | Three dimensional(3D) memory device sparing | Edgar R. Cordero, Anil B. Lingambudi, Kenneth L. Wright | 2014-10-28 |
| 8869007 | Three dimensional (3D) memory device sparing | Edgar R. Cordero, Anil B. Lingambudi, Kenneth L. Wright | 2014-10-21 |
| 8853847 | Stacked chip module with integrated circuit chips having integratable and reconfigurable built-in self-maintenance blocks | Kevin W. Gorman, Krishnendu Mondal | 2014-10-07 |
| 8848470 | Memory operation upon failure of one of two paired memory devices | Edgar R. Cordero, Timothy J. Dell, Girisankar Paulraj | 2014-09-30 |
| 8676559 | System and method for providing efficient schematic review | John Francis Mullen | 2014-03-18 |
| 8589776 | Translation between a first communication protocol and a second communication protocol | Jean Calvignac, Daniel G. Eisenhauer, Ashish A. More, Anil Pothireddy, Christoph Raisch +2 more | 2013-11-19 |
| 8552291 | Cable for high speed data communications | Anil B. Lingambudi, Bhyrav M. Mutnury, Nam H. Pham | 2013-10-08 |
| 7979823 | Identification of voltage reference errors in PCB designs | Anil B. Lingambudi, Anandavally Sreekala | 2011-07-12 |
| 7921404 | Method of reusing constraints in PCB designs | Anil B. Lingambudi, Ankur Kanu Patel, Diyanesh Vidyapoornachary Babu Chinnakkonda | 2011-04-05 |