Issued Patents All Time
Showing 1–19 of 19 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11579890 | Frame parser executing subsets of instructions in parallel for processing a frame header | Mehulkumar Kantibhai Gor, Lokesh Kabra | 2023-02-14 |
| 9667564 | Implementing hierarchical high radix switch with timesliced crossbar | Nikolaos Chrysos, Girish G. Kurup, Cyriel Minkenberg, Mark L. Rudquist, Vibhor K. Srivastava +1 more | 2017-05-30 |
| 9479455 | Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar | Nikolaos Chrysos, Girish Gopala Kurup, Cyriel J. Minkenberg, Vibhor K. Srivastava, Brian T. Vanderpool | 2016-10-25 |
| 9467396 | Simultaneous transfers from a single input link to multiple output links with a timesliced crossbar | Nikolaos Chrysos, Girish Gopala Kurup, Cyriel J. Minkenberg, Vibhor K. Srivastava, Brian T. Vanderpool | 2016-10-11 |
| 9207999 | Integrated link-based data recorder for semiconductor chip | Scott Douglas Clark, Ashish A. More, Sudheendra Srivathsa, Brian T. Vanderpool | 2015-12-08 |
| 9110742 | Integrated link-based data recorder for semiconductor chip | Scott Douglas Clark, Ashish A. More, Sudheendra Srivathsa, Brian T. Vanderpool | 2015-08-18 |
| 8984206 | Weightage-based scheduling for hierarchical switching fabrics | Nikolaos Chrysos, Girish Gopala Kurup, Cyriel Minkenberg, Vibhor K. Srivastava, Brian T. Vanderpool | 2015-03-17 |
| 8902750 | Translating between an ethernet protocol and a converged enhanced ethernet protocol | Claude Basso, Christoph Raisch, Saravanan Sethuraman, Vibhor K. Srivastava, Jan-Bernd Themann +1 more | 2014-12-02 |
| 8902899 | Input buffered switching device including bypass logic | Nikolaos Chrysos, Brian T. Vanderpool | 2014-12-02 |
| 8589776 | Translation between a first communication protocol and a second communication protocol | Jean Calvignac, Daniel G. Eisenhauer, Ashish A. More, Christoph Raisch, Saravanan Sethuraman +2 more | 2013-11-19 |
| 8316187 | Cache memory including a predict buffer | — | 2012-11-20 |
| 8161366 | Finite state machine error recovery | Neranjen Ramalingam | 2012-04-17 |
| 8132036 | Reducing latency in data transfer between asynchronous clock domains | Kirtish Karlekar, David Grant Wheeler | 2012-03-06 |
| 7916048 | Encoding a gray code sequence for an odd length sequence | Jayashri Arsikere Basappa, David Grant Wheeler | 2011-03-29 |
| 7870448 | In system diagnostics through scan matrix | Baalaji Ramamoorthy Konda, Kenneth Pichamuthu, Jayashri Arsikere Basappa | 2011-01-11 |
| 7853738 | Efficient load/store buffer memory management in a computer communications network data transmission switch | Jayashri Arsikere Basappa, Gopikrishnan Viswanadhan, Neranjen Ramalingam | 2010-12-14 |
| 7667629 | Generating a gray code for an odd length sequence using a virtual space | Jayashri Arsikere Basappa, David Grant Wheeler | 2010-02-23 |
| 7518535 | Generating a Gray code sequence for any even length using an intermediate binary sequence | Jayashri Arsikere Basappa, David Grant Wheeler | 2009-04-14 |
| 7500132 | Method of asynchronously transmitting data between clock domains | Kirtish Karlekar, Grant Wheeler | 2009-03-03 |