Issued Patents All Time
Showing 51–75 of 75 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7552407 | Method and system for performing target enlargement in the presence of constraints | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2009-06-23 |
| 7509605 | Extending incremental verification of circuit design to encompass verification restraints | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2009-03-24 |
| 7480877 | Methods and apparatus for Boolean equivalency checking in the presence of voting logic | Victor A. Acuna, Scott Mack, Brian C. Wilson | 2009-01-20 |
| 7478344 | Method and system for enhanced verification by closely coupling a structural satisfiability solver and rewriting algorithms | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2009-01-13 |
| 7448005 | Method and system for performing utilization of traces for incremental refinement in coupling a structural overapproximation algorithm and a satisfiability solver | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-11-04 |
| 7398488 | Trace equivalence identification through structural isomorphism detection with on the fly logic writing | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-07-08 |
| 7380221 | Method and system for reduction of and/or subexpressions in structural design representations | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-05-27 |
| 7380222 | Method and system for performing minimization of input count during structural netlist overapproximation | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-05-27 |
| 7373624 | Method and system for performing target enlargement in the presence of constraints | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-05-13 |
| 7370292 | Method for incremental design reduction via iterative overapproximation and re-encoding strategies | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-05-06 |
| 7360185 | Design verification using sequential and combinational transformations | Jason Raymond Baumgarter, Hari Mony, Viresh Paruthi | 2008-04-15 |
| 7356792 | Method and system for enhanced verification by closely coupling a structural overapproximation algorithm and a structural satisfiability solver | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-04-08 |
| 7350169 | Method and system for enhanced verification through structural target decomposition | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-03-25 |
| 7343573 | Method and system for enhanced verification through binary decision diagram-based target decomposition | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-03-11 |
| 7340694 | Method and system for reduction of XOR/XNOR subexpressions in structural design representations | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-03-04 |
| 7315996 | Method and system for performing heuristic constraint simplification | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2008-01-01 |
| 7266795 | System and method for engine-controlled case splitting within multiple-engine based verification framework | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2007-09-04 |
| 7260799 | Exploiting suspected redundancy for enhanced design verification | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2007-08-21 |
| 7210109 | Equivalence checking of scan path flush operations | Kenneth Michael Caron, Scott Mack, Lance G. Thompson, Mark A. Williams | 2007-04-24 |
| 7093218 | Incremental, assertion-based design verification | Jason R. Baumgartner, Hari Mony, Viresh Paruthi | 2006-08-15 |
| 6763505 | Apparatus and method for automated use of phase abstraction for enhanced verification of circuit designs | Jason R. Baumgartner, Wolfgang Roesner | 2004-07-13 |
| 6748573 | Apparatus and method for removing effects of phase abstraction from a phase abstracted trace | Jason R. Baumgartner, Wolfgang Roesner | 2004-06-08 |
| 6745377 | Apparatus and method for representing gated-clock latches for phase abstraction | Jason R. Baumgartner, Wolfgang Roesner | 2004-06-01 |
| 5799170 | Simplified buffer manipulation using standard repowering function | Anthony D. Drumm, Bruce George Rudolph | 1998-08-25 |
| 5537330 | Method for mapping in logic synthesis by logic classification | Robert F. Damiano, Anthony D. Drumm, Michael Kay Edwards, Kathy M. McCarthy | 1996-07-16 |