Issued Patents All Time
Showing 151–157 of 157 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7249331 | Architectural level throughput based power modeling methodology and apparatus for pervasively clock-gated processor cores | Tejas Karkhanis, Srinivasan Ramani, Malcolm S. Ware, Ken V. Vu | 2007-07-24 |
| 7134028 | Processor with low overhead predictive supply voltage gating for leakage power reduction | David M. Brooks, Peter W. Cook, Philip G. Emma, Michael K. Gschwind, Stanley E. Schuster +1 more | 2006-11-07 |
| 7076681 | Processor with demand-driven clock throttling power reduction | Daniel Citron, Peter W. Cook, Philip G. Emma, Hans M. Jacobson, Prabhakar Kudva +3 more | 2006-07-11 |
| 7065665 | Interlocked synchronous pipeline clock gating | Hans M. Jacobson, Prabhakar Kudva, Peter W. Cook, Stanley E. Schuster | 2006-06-20 |
| 6946869 | Method and structure for short range leakage control in pipelined circuits | Hans M. Jacobson, Alper Buyuktosunoglu, Peter W. Cook, Philip G. Emma, Prabhakar Kudva +1 more | 2005-09-20 |
| 6059835 | Performance evaluation of processor operation using trace pre-processing | — | 2000-05-09 |
| 5805876 | Method and system for reducing average branch resolution time and effective misprediction penalty in a processor | Kin Shing Chan, Hung Q. Le, Robert Eric Wasmuth | 1998-09-08 |