Issued Patents All Time
Showing 126–150 of 151 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7626220 | Semiconductor scheme for reduced circuit area in a simplified process | Todd A. Christensen, Richard Lee Donze, William Paul Hovis, Terrance Wayne Kueper | 2009-12-01 |
| 7541829 | Method for correcting for asymmetry of threshold voltage shifts | Ronald J. Bolam, Terrance Wayne Kueper, David P. Paulsen | 2009-06-02 |
| 7514276 | Aligning stacked chips using resistance assistance | Corey Elizabeth Yearous, Phil C. Paone, Kelly L. Williams, David P. Paulsen, Gregory J. Uhlmann +1 more | 2009-04-07 |
| 7453272 | Electrical open/short contact alignment structure for active region vs. gate region | Richard Lee Donze, Karl R. Erickson, William Paul Hovis, Jon Robert Tetzloff | 2008-11-18 |
| 7336086 | Measurement of bias of a silicon area using bridging vertices on polysilicon shapes to create an electrical open/short contact structure | Richard Lee Donze, Karl R. Erickson, William Paul Hovis, Jon Robert Tetzloff | 2008-02-26 |
| 7317217 | Semiconductor scheme for reduced circuit area in a simplified process | Todd A. Christensen, Richard Lee Donze, William Paul Hovis, Terrance Wayne Kueper | 2008-01-08 |
| 7317605 | Method and apparatus for improving performance margin in logic paths | Richard Lee Donze, William Paul Hovis, Terrance Wayne Kueper, Jon Robert Tetzloff | 2008-01-08 |
| 7241649 | FinFET body contact structure | Richard Lee Donze, Karl R. Erickson, William Paul Hovis, Terrance Wayne Kueper, Jon Robert Tetzloff | 2007-07-10 |
| 7227183 | Polysilicon conductor width measurement for 3-dimensional FETs | Richard Lee Donze, William Paul Hovis, Terrance Wayne Kueper, Jon Robert Tetzloff | 2007-06-05 |
| 7183780 | Electrical open/short contact alignment structure for active region vs. gate region | Richard Lee Donze, Karl R. Erickson, William Paul Hovis, Jon Robert Tetzloff | 2007-02-27 |
| 7050871 | Method and apparatus for implementing silicon wafer chip carrier passive devices | Gerald K. Bartley, Darryl J. Becker, Paul Eric Dahlen, Philip Raymond Germann, Andrew Benson Maki +1 more | 2006-05-23 |
| 7009905 | Method and apparatus to reduce bias temperature instability (BTI) effects | Anthony Gus Aipperspach, William Paul Hovis, Terrance Wayne Kueper | 2006-03-07 |
| 6774734 | Ring oscillator circuit for EDRAM/DRAM performance monitoring | Todd A. Christensen, Terrance Wayne Kueper | 2004-08-10 |
| 6670716 | Silicon-on-insulator (SOI) semiconductor structure for implementing transistor source connections using buried dual rail distribution | Todd A. Christensen, Gregory J. Uhlmann | 2003-12-30 |
| 6667518 | Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices | Todd A. Christensen | 2003-12-23 |
| 6645796 | Method and semiconductor structure for implementing reach through buried interconnect for silicon-on-insulator (SOI) devices | Todd A. Christensen | 2003-11-11 |
| 6635518 | SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologies | Anthony Gus Aipperspach, Jente B. Kuang, Daniel Stasiak | 2003-10-21 |
| 6528853 | Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors | Todd A. Christensen | 2003-03-04 |
| 6498057 | Method for implementing SOI transistor source connections using buried dual rail distribution | Todd A. Christensen, Gregory J. Uhlmann | 2002-12-24 |
| 6492244 | Method and semiconductor structure for implementing buried dual rail power distribution and integrated decoupling capacitance for silicon on insulator (SOI) devices | Todd A. Christensen | 2002-12-10 |
| 6429099 | Implementing contacts for bodies of semiconductor-on-insulator transistors | Todd A. Christensen | 2002-08-06 |
| 6287901 | Method and semiconductor structure for implementing dual plane body contacts for silicon-on-insulator (SOI) transistors | Todd A. Christensen | 2001-09-11 |
| 6121659 | Buried patterned conductor planes for semiconductor-on-insulator integrated circuit | Todd A. Christensen | 2000-09-19 |
| 6043689 | Driver circuit for providing reduced AC defects | Robert R. Williams | 2000-03-28 |
| 5889306 | Bulk silicon voltage plane for SOI applications | Todd A. Christensen | 1999-03-30 |