Issued Patents All Time
Showing 26–38 of 38 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7176725 | Fast pulse powered NOR decode apparatus for semiconductor devices | Donald W. Plass, Kenneth J. Reyer | 2007-02-13 |
| 7170320 | Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering | Thomas J. Knips, Donald W. Plass, Kenneth J. Reyer | 2007-01-30 |
| 7099206 | High density bitline selection apparatus for semiconductor memory devices | Donald W. Plass, Kenneth J. Reyer | 2006-08-29 |
| 7088638 | Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays | Paul A. Bunce, John D. Davis, Donald W. Plass | 2006-08-08 |
| 7076710 | Non-binary address generation for ABIST | Thomas J. Knips, Tom Chang, Douglas J. Malone | 2006-07-11 |
| 7073105 | ABIST address generation | Thomas J. Knips, John D. Davis, Douglas J. Malone | 2006-07-04 |
| 7068554 | Apparatus and method for implementing multiple memory redundancy with delay tracking clock | Thomas J. Knips, Donald W. Plass, Kenneth J. Reyer | 2006-06-27 |
| 7064990 | Method and apparatus for implementing multiple column redundancy for memory | Thomas J. Knips, Donald W. Plass, Kenneth J. Reyer | 2006-06-20 |
| 6728912 | SOI cell stability test method | Paul A. Bunce, Donald W. Plass | 2004-04-27 |
| 5313424 | Module level electronic redundancy | Robert Dean Adams, Henry A. Bonges, III, Erik L. Hedberg | 1994-05-17 |
| 5206583 | Latch assisted fuse testing for customized integrated circuits | George A. DeLuca, Michael Nicewicz | 1993-04-27 |
| 4995001 | Memory cell and read circuit | Panagiotis A. Phillips | 1991-02-19 |
| 4644680 | Transmitter rod | — | 1987-02-24 |