Issued Patents All Time
Showing 76–94 of 94 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7514276 | Aligning stacked chips using resistance assistance | Corey Elizabeth Yearous, Phil C. Paone, Kelly L. Williams, David P. Paulsen, John E. Sheets, II +1 more | 2009-04-07 |
| 7489572 | Method for implementing eFuse sense amplifier testing without blowing the eFuse | Anthony Gus Aipperspach, David H. Allen, Louis Bernard Bushard, Phil C. Paone | 2009-02-10 |
| 7224633 | eFuse sense circuit | William Paul Hovis, Alan J. Leslie, Phil C. Paone, David W. Siljenberg, Salvatore N. Storino | 2007-05-29 |
| 7203518 | Method and apparatus for simplified data dispensation to and from digital systems | Salvatore N. Storino | 2007-04-10 |
| 7088994 | Network address lookup for telephony devices | — | 2006-08-08 |
| 6928009 | Redundancy circuit for memory array and method for disabling non-redundant wordlines and for enabling redundant wordlines | Chad A. Adams | 2005-08-09 |
| 6895215 | Method and apparatus for transferring correspondence information | — | 2005-05-17 |
| 6748556 | Changing the thread capacity of a multithreaded computer processor | Salvatore N. Storino | 2004-06-08 |
| 6681345 | Field protection against thread loss in a multithreaded computer processor | Salvatore N. Storino | 2004-01-20 |
| 6670716 | Silicon-on-insulator (SOI) semiconductor structure for implementing transistor source connections using buried dual rail distribution | Todd A. Christensen, John E. Sheets, II | 2003-12-30 |
| 6629236 | Master-slave latch circuit for multithreaded processing | Anthony Gus Aipperspach, Merwin H. Alferness | 2003-09-30 |
| 6498057 | Method for implementing SOI transistor source connections using buried dual rail distribution | Todd A. Christensen, John E. Sheets, II | 2002-12-24 |
| 6266800 | System and method for eliminating effects of parasitic bipolar transistor action in dynamic logic using setup time determination | Salvatore N. Storino | 2001-07-24 |
| 6211713 | Adjustable feedback for CMOS latches | — | 2001-04-03 |
| 6163173 | Method and apparatus for implementing adjustable logic threshold in dynamic circuits for maximizing circuit performance | Salvatore N. Storino, Robert R. Williams | 2000-12-19 |
| 6084810 | Dynamic logic circuit with bitline repeater circuit | Salvatore N. Storino | 2000-07-04 |
| 6060909 | Compound domino logic circuit including an output driver section with a latch | Anthony Gus Aipperspach | 2000-05-09 |
| 5973971 | Device and method for verifying independent reads and writes in a memory array | Salvatore N. Storino | 1999-10-26 |
| 5778243 | Multi-threaded cell for a memory | Anthony Gus Aipperspach, Todd A. Christensen, Binta M. Patel, Nghia Van Phan, Michael J. Rohn +2 more | 1998-07-07 |