Issued Patents All Time
Showing 26–50 of 56 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7606060 | Eight transistor SRAM cell with improved stability requiring only one word line | Yuen H. Chan, William V. Huott | 2009-10-20 |
| 7471590 | Write control circuitry and method for a memory array configured with multiple memory subarrays | John D. Davis, Paul A. Bunce, Kenneth J. Reyer | 2008-12-30 |
| 7437626 | Efficient method of test and soft repair of SRAM with redundancy | Tom Chang, William V. Huott, Thomas J. Knips | 2008-10-14 |
| 7403412 | Integrated circuit chip with improved array stability | Yuen H. Chan, Rajiv V. Joshi | 2008-07-22 |
| 7380191 | ABIST data compression and serialization for memory built-in self test of SRAM with redundancy | James Dawson, Thomas J. Knips, Kenneth J. Reyer | 2008-05-27 |
| 7299374 | Clock control method and apparatus for a memory array | James Dawson, Paul A. Bunce, Kenneth J. Reyer | 2007-11-20 |
| 7295458 | Eight transistor SRAM cell with improved stability requiring only one word line | Yuen H. Chan, William V. Huott | 2007-11-13 |
| 7295457 | Integrated circuit chip with improved array stability | Yuen H. Chan, Rajiv V. Joshi | 2007-11-13 |
| 7283417 | Write control circuitry and method for a memory array configured with multiple memory subarrays | John D. Davis, Paul A. Bunce, Kenneth J. Reyer | 2007-10-16 |
| 7266737 | Method for enabling scan of defective ram prior to repair | Paul A. Bunce, John D. Davis, Patrick J. Meaney | 2007-09-04 |
| 7233542 | Method and apparatus for address generation | Paul A. Bunce, John D. Davis | 2007-06-19 |
| 7219275 | Method and apparatus for providing flexible modular redundancy allocation for memory built in self test of SRAM with redundancy | Tom Chang, William V. Huott, Thomas J. Knips | 2007-05-15 |
| 7210084 | Integrated system logic and ABIST data compression for an SRAM directory | Paul A. Bunce, John D. Davis, Thomas J. Knips | 2007-04-24 |
| 7176725 | Fast pulse powered NOR decode apparatus for semiconductor devices | James Dawson, Kenneth J. Reyer | 2007-02-13 |
| 7173875 | SRAM array with improved cell stability | Yuen H. Chan, Rajiv V. Joshi | 2007-02-06 |
| 7170320 | Fast pulse powered NOR decode apparatus with pulse stretching and redundancy steering | James Dawson, Thomas J. Knips, Kenneth J. Reyer | 2007-01-30 |
| 7102944 | Programmable analog control of a bitline evaluation circuit | Paul A. Bunce, John D. Davis | 2006-09-05 |
| 7099203 | Circuit and method for writing a binary value to a memory cell | Paul A. Bunce, John D. Davis | 2006-08-29 |
| 7099206 | High density bitline selection apparatus for semiconductor memory devices | James Dawson, Kenneth J. Reyer | 2006-08-29 |
| 7088638 | Global and local read control synchronization method and system for a memory array configured with multiple memory subarrays | Paul A. Bunce, John D. Davis, James Dawson | 2006-08-08 |
| 7085173 | Write driver circuit for memory array | Paul A. Bunce, John D. Davis | 2006-08-01 |
| 7075855 | Memory output timing control circuit with merged functions | Paul A. Bunce, John D. Davis | 2006-07-11 |
| 7068554 | Apparatus and method for implementing multiple memory redundancy with delay tracking clock | James Dawson, Thomas J. Knips, Kenneth J. Reyer | 2006-06-27 |
| 7064990 | Method and apparatus for implementing multiple column redundancy for memory | James Dawson, Thomas J. Knips, Kenneth J. Reyer | 2006-06-20 |
| 7023759 | System and method for synchronizing memory array signals | Paul A. Bunce, John D. Davis | 2006-04-04 |