Issued Patents All Time
Showing 26–33 of 33 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7076749 | Method and system for improving integrated circuit manufacturing productivity | Douglas W. Kemerer, Gustavo E. Tellez, Lijiang Wang, Peter S. Wissell | 2006-07-11 |
| 6823496 | Physical design characterization system | Bette L. Bergman Reuter, Mitchell R. DeHond, William C. Leipold, Brian D. Pfeifer, David C. Reynolds +1 more | 2004-11-23 |
| 6738954 | Method for prediction random defect yields of integrated circuits with accuracy and computation time controls | Archibald J. Allen, Wilm E. Donath, Alan Dziedzic, Mark A. Lavin, Dennis M. Newns +1 more | 2004-05-18 |
| 6394638 | Trench isolation for active areas and first level conductors | Edward W. Sengle, Mark D. Jaffe, Mark A. Lavin, Eric J. White, John A. Bracchitta | 2002-05-28 |
| 6063687 | Formation of trench isolation for active areas and first level conductors | Edward W. Sengle, Mark D. Jaffe, Mark A. Lavin, Eric J. White, John A. Bracchitta | 2000-05-16 |
| 6021267 | Aspect ratio program for optimizing semiconductor chip shape | Jeffrey P. Bonn, Sharon B. Sisler, Richard Charles Whiteside | 2000-02-01 |
| 5734192 | Trench isolation for active areas and first level conductors | Edward W. Sengle, Mark D. Jaffe, Mark A. Lavin, Eric J. White, John A. Bracchitta | 1998-03-31 |
| 5636133 | Efficient generation of fill shapes for chips and packages | Donald G. Chesebro, Young Ouk Kim, Mark A. Lavin | 1997-06-03 |