Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10014280 | Three dimensional fully molded power electronics module having a plurality of spacers for high power applications | Ziyang Gao, Shi Wo Chow | 2018-07-03 |
| 9075941 | Method for optimizing electrodeposition process of a plurality of vias in wafer | Yaofeng Sun, Bin Xie, Ou Dong | 2015-07-07 |
| 9066424 | Partitioned hybrid substrate for radio frequency applications | Dan Yang, Song He, Yuxing Ren | 2015-06-23 |
| 8772930 | Increased surface area electrical contacts for microelectronic packages | Pui Chung Simon Law, Dan Yang | 2014-07-08 |
| 8674482 | Semiconductor chip with through-silicon-via and sidewall pad | Bin Xie, Chang Hwa Chung | 2014-03-18 |
| 8544165 | Apparatus for aligning electronic components | Chi Kuen Vincent Leung, Bin Xie | 2013-10-01 |
| 8232626 | Via and method of via forming and method of via filling | Yat Kit Tsui, Dan Yang | 2012-07-31 |
| 8212297 | High optical efficiency CMOS image sensor | Pui Chung Simon Law, Dan Yang | 2012-07-03 |
| 8194411 | Electronic package with stacked modules with channels passing through metal layers of the modules | Chi Kuen Vincent Leung, Peng SUN, Chang Hwa Chung | 2012-06-05 |
| 8138577 | Pulse-laser bonding method for through-silicon-via based stacking of electronic components | Wei Ma, Bin Xie, Chang Hwa Chung | 2012-03-20 |
| 8030208 | Bonding method for through-silicon-via based 3D wafer stacking | Chi Kuen Vincent Leung, Peng SUN, Chang Hwa Chung | 2011-10-04 |
| 7879438 | Substrate warpage-reducing structure | Jyh-Rong Lin, Bin Xie, Yeung Yeung, Chang Hwa Chung | 2011-02-01 |