Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6512257 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon | 2003-01-28 |
| 6396088 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon | 2002-05-28 |
| 6339358 | Semiconductor integrated circuit | Masashi Horiguchi, Yasushi Kawase, Yoshinobu Nakagome, Kazuhiko Kajigaya | 2002-01-15 |
| 6288925 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon | 2001-09-11 |
| 6115279 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon | 2000-09-05 |
| 6107869 | Semiconductor integrated circuit | Masashi Horiguchi, Yasushi Kawase, Yoshinobu Nakagome, Kazuhiko Kajigaya | 2000-08-22 |
| 6069813 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon | 2000-05-30 |
| 6028800 | Sense amplifier driver having variable power-supply voltage | Goro Kitsukawa, Hiroshi Otori, Masayuki Nakamura, Hideo Sunami, Adin E. Hyslop | 2000-02-22 |
| 5995404 | DRAM architecture with aligned data storage and bond pads | Masayuki Nakaumura, Brent Haukness | 1999-11-30 |
| 5966341 | Semiconductor memory | Tsugio Takahashi, Goro Kitsukawa, Yasushi Kawase, Masayuki Nakamura | 1999-10-12 |
| 5953242 | System with meshed power and signal buses on cell array | Goro Kitsukawa, Hiroshi Otori, William R. McKee, Jeffrey E. Koelling, Troy H. Herndon | 1999-09-14 |
| 5881005 | Semiconductor integrated circuit device having a constant delay-time circuit for different operating voltages | Hiroshi Otori | 1999-03-09 |
| 5859807 | Semiconductor integrated circuit device having a controlled overdriving circuit | Hiroshi Otori, Goro Kitsukawa, Hugh P. McAdams | 1999-01-12 |
| 5844853 | Memory regulator control method with flexibility for a wide change in supply voltage | Goro Kitsukawa, Wah Kit Loh, Masayuki Nakamura, Hiroshi Otori | 1998-12-01 |
| 5793694 | Semiconductor integrated circuit device having means for peak current reduction | Hiroshi Otori, Masayuki Nakamura, Adin E. Hyslop | 1998-08-11 |
| 5777927 | Semiconductor memory | Tsugio Takahashi, Goro Kitsukawa, Yasushi Kawase, Masayuki Nakamura | 1998-07-07 |
| 5703825 | Semiconductor integrated circuit device having a leakage current reduction means | Goro Kitsukawa | 1997-12-30 |
| 5604697 | Semiconductor | Tsugio Takahashi, Goro Kitsukawa, Yasushi Kawase, Masayuki Nakamura | 1997-02-18 |
| 5448526 | Semiconductor integrated circuit device | Masashi Horiguchi, Kiyoo Itoh, Yoshiki Kawajiri, Goro Kitsukawa, Takayuki Kawahara | 1995-09-05 |
| 5347492 | Semiconductor integrated circuit device | Masashi Horiguchi, Kiyoo Itoh, Yoshiki Kawajiri, Goro Kitsukawa, Takayuki Kawahara | 1994-09-13 |
| 5337271 | Semiconductor storage device capable of reduced current consumption using a charge reuse circuit | Takayuki Kawahara, Yoshiki Kawajiri, Mssashi Horiguchi, Goro Kitsukawa, Masakazu Aoki | 1994-08-09 |
| 5300839 | Semiconductor IC device having sense amplifier circuit | Takayuki Kawahara, Goro Kitsukawa, Yoshiki Kawajiri, Kiyoo Itoh, Takeshi Sakata | 1994-04-05 |
| 5289425 | Semiconductor integrated circuit device | Masashi Horiguchi, Kiyoo Itoh, Yoshiki Kawajiri, Goro Kitsukawa, Takayuki Kawahara | 1994-02-22 |
| 5274601 | Semiconductor integrated circuit having a stand-by current reducing circuit | Takayuki Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takao Watanabe, Goro Kitsukawa +3 more | 1993-12-28 |
| 4873672 | Dynamic random access memory capable of fast erasing of storage data | Jun Etoh, Katsuhiro Shimohigashi, Kazuyuki Miyazawa, Katsutaka Kimura | 1989-10-10 |