Issued Patents All Time
Showing 26–50 of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6590425 | Semiconductor integrated circuit apparatus | Fumio Murabayashi, Tatsumi Yamauchi, Hiromichi Yamada | 2003-07-08 |
| 6587927 | Data processor having cache memory | Toshihiko Kurihara, Shigeya Tanaka, Hideo Sawamoto, Akiyoshi Osumi, Koji Saito +1 more | 2003-07-01 |
| 6557439 | Driving force distributing structure for four wheel drive vehicle | Tetsuya Ohtani, Tadayasu Sanpe, Nobuo Takemasa | 2003-05-06 |
| 6520041 | Three parallel shaft type automatic transmission | Moriaki Tokuda, Fumihiro YOSHINO, Shuji Ueda, Tetsu Kanou | 2003-02-18 |
| 6484294 | Semiconductor integrated circuit and method of designing the same | Yoshikazu Kiyoshige, Michinobu Nakao, Kazumi Hatayama | 2002-11-19 |
| 6467004 | Pipelined semiconductor devices suitable for ultra large scale integration | Masahiro Iwamura, Shigeya Tanaka, Tatsumi Yamauchi, Kazutaka Mori | 2002-10-15 |
| 6437621 | Waveform shaping device | Kazuo Kato, Takashi Sase, Fumio Murabayashi | 2002-08-20 |
| 6389041 | Synchronization system and synchronization method of multisystem control apparatus | Yuichiro Morita, Kotaro Shimamura, Yoshitaka Takahashi, Kazuhiro Imaie, Shigeta Ueda +3 more | 2002-05-14 |
| 6385755 | Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them | Tetsuya Shimomura, Fumio Murabayashi, Kotaro Shimamura, Nobuyasu Kanekawa | 2002-05-07 |
| 6275902 | Data processor with variable types of cache memories and a controller for selecting a cache memory to be access | Toshihiko Kurihara, Shigeya Tanaka, Hideo Sawamoto, Akiyoshi Osumi, Koji Saito +1 more | 2001-08-14 |
| 6256726 | Data processor for the parallel processing of a plurality of instructions | Shigeya Tanaka, Hideo Maejima | 2001-07-03 |
| 6249608 | Template matching image processor utilizing sub image pixel sums and sum of squares thresholding | Mitsuji Ikeda, Syoji Yoshida, Keisuke Nakashima, Koyo Katsura, Shigeru Shibukawa +1 more | 2001-06-19 |
| 6101627 | Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them | Tetsuya Shimomura, Fumio Murabayashi, Kotaro Shimamura, Nobuyasu Kanekawa | 2000-08-08 |
| 6101596 | Information processor for performing processing without register conflicts | Shigeya Tanaka, Kotaro Shimamura, Tetsuya Shimomura, Hideo Sawamoto | 2000-08-08 |
| 6038683 | Replicated controller and fault recovery method thereof | Kotaro Shimamura, Yuuichiro Morita, Yoshitaka Takahashi, Hiroyasu Satou, Shigeta Ueda +3 more | 2000-03-14 |
| 6033335 | Planetary gear mechanism | Tadami Kondoh, Motonori Ohnuki, Kazuya Kubo | 2000-03-07 |
| 6032229 | Semiconductor memory device and information processor using the same | Hideo Sawamoto, Noboru Akiyama, Takashi Akioka, Shigeya Tanaka | 2000-02-29 |
| 6029220 | Pipelined semiconductor devices suitable for ultra large scale integration | Masahiro Iwamura, Shigeya Tanaka, Tatsumi Yamauchi, Kazutaka Mori | 2000-02-22 |
| 6007448 | Lubrication structure for planetary gear assembly | Takamichi Shimada | 1999-12-28 |
| 5974560 | Information processor and information processing system utilizing clock signal | Kozaburo Kurita, Masahiro Iwamura, Hideo Maejima, Shigeya Tanaka, Tadaaki Bandoh +3 more | 1999-10-26 |
| 5968160 | Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory | Masahiko Saito, Kenichi Kurosawa, Yoshiki Kobayashi, Tadaaki Bandoh, Masahiro Iwamura +3 more | 1999-10-19 |
| 5935037 | Planetary gear transmission | Takamichi Shimada | 1999-08-10 |
| 5894582 | Method of controlling parallel processing at an instruction level and processor for realizing the method | Shoji Yoshida, Shigeya Tanaka | 1999-04-13 |
| 5848432 | Data processor with variable types of cache memories | Toshihiko Kurihara, Shigeya Tanaka, Hideo Sawamoto, Akiyoshi Osumi, Koji Saito +1 more | 1998-12-08 |
| 5848238 | Information processing system and logic LSI, detecting a fault in the system or the LSI, by using internal data processed in each of them | Tetsuya Shimomura, Fumio Murabayashi, Kotaro Shimamura, Nobuyasu Kanekawa | 1998-12-08 |