Issued Patents All Time
Showing 26–48 of 48 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6425039 | Accessing exception handlers without translating the address | Ikuya Kawasaki, Shigezumi Matsui, Susumu Narita | 2002-07-23 |
| 6412043 | Microprocessor having improved memory management unit and cache memory | Rajesh Chopra, Mark Debbage, David Shepherd | 2002-06-25 |
| 6389523 | Cache memory employing dynamically controlled data array start timing and a microprocessor using the same | Yasuhisa Shimazaki, Seiichi Nagata, Katuhiro Norisue, Koichiro Ishibashi, Junichi Nishimoto +1 more | 2002-05-14 |
| 6324634 | Methods for operating logical cache memory storing logical and physical address information | Shumpei Kawasaki | 2001-11-27 |
| 6138226 | Logical cache memory storing logical and physical address information for resolving synonym problems | Shumpei Kawasaki | 2000-10-24 |
| 6085211 | Logic circuit and floating-point arithmetic unit | — | 2000-07-04 |
| 6070234 | Cacche memory employing dynamically controlled data array start timing and a microcomputer using the same | Yasuhisa Shimazaki, Seiichi Nagata, Katuhiro Norisue, Koichiro Ishibashi, Junichi Nishimoto +1 more | 2000-05-30 |
| 6047354 | Data processor for implementing virtual pages using a cache and register | Ikuya Kawasaki, Susumu Narita, Saneaki Tamaki | 2000-04-04 |
| 6038661 | Single-chip data processor handling synchronous and asynchronous exceptions by branching from a first exception handler to a second exception handler | Ikuya Kawasaki, Shigezumi Matsui, Susumu Narita | 2000-03-14 |
| 5939947 | Phase synchronous circuit | Takehiko Nakao | 1999-08-17 |
| 5930833 | Logical cache memory storing logical and physical address information for resolving synonym problems | Shumpei Kawasaki | 1999-07-27 |
| 5907867 | Translation lookaside buffer supporting multiple page sizes | Toshinobu Shinbo, Suguru Tachibana, Susumu Narita, Koichiro Ishibashi, Hisayuki Higuchi +3 more | 1999-05-25 |
| 5860127 | Cache memory employing dynamically controlled data array start timing and a microcomputer using the same | Yasuhisa Shimazaki, Seiichi Nagata, Katuhiro Norisue, Koichiro Ishibashi, Junichi Nishimoto +1 more | 1999-01-12 |
| 5845109 | Operation unit and method for controlling processing speed of the same | Seigo Suzuki | 1998-12-01 |
| 5835963 | Processor with an addressable address translation buffer operative in associative and non-associative modes | Susumu Narita, Ikuya Kawasaki, Saneaki Tamaki | 1998-11-10 |
| 5796978 | Data processor having an address translation buffer operable with variable page sizes | Ikuya Kawasaki, Susumu Narita, Saneaki Tamaki | 1998-08-18 |
| 5781048 | Synchronous circuit capable of properly removing in-phase noise | Takehiko Nakao | 1998-07-14 |
| 5774701 | Microprocessor operating at high and low clok frequencies | Shigezumi Matsui, Mitsuyoshi Yamamoto, Susumu Narita, Ikuya Kawasaki, Susumu Kaneko +1 more | 1998-06-30 |
| 5515519 | Data processor and method utilizing coded no-operation instructions | Fumio Arakawa, Hiroshi Yajima, Yugo Kashiwagi | 1996-05-07 |
| 5449544 | Weather strip for an automobile and a method for assembling the same | Kazuo Ogawa, Masahiro Koide, Masahiro Nozaki | 1995-09-12 |
| 5389409 | Weatherstrip | Tadanobu Iwasa, Keiji Akachi, Toshiyuki Tanaka | 1995-02-14 |
| 5141983 | Aqueous coating composition | Yoshiki Hasegawa, Fumio Yoshino, Kiyoshi Ohnishi | 1992-08-25 |
| 4973614 | Process for producing emulsion polymer composition | Fumio Yoshino, Yoshiki Hasegawa | 1990-11-27 |